JEDEC SPHBM4 New Standard to Deliver HBM4-Level Throughput with Reduced Pin Count

JEDEC Solid State Technology Association announced it is nearing completion of a new standard for Standard Package High Bandwidth Memory (SPHBM4).

SPHBM4 devices are similar to the HBM4 devices commonly used in AI accelerators, using the same DRAM dies on a new interface base die which can be mounted on standard organic substrates. In contrast, HBM4 is typically mounted on silicon substrates.

As planned, SPHBM operates at the same aggregate data throughput as HBM4 using fewer pins by operating at a higher frequency. Where the HBM4 interface has 2,048 data signals, when published, SPHBM4 will define 512 data signals with 4:1 serialization to achieve the same bandwidth. This change allows the relaxed bump pitch required for connection to organic substrates.

Since SPHBM4 uses the same memory core layers as HBM4, total memory capacity/stack capability is identical. However, an added benefit of organic substrate routing is a longer supported channel length from the SoC to the memory, potentially increasing the total number of SPHBM stacks and therefore total memory capacity.

Stay tuned for more updates and details when SPHBM4 standard is published. For access to pre-publication proposals and early insights into active projects such as SPHBM4, consider joining JEDEC as a member company.

“JEDEC members are actively shaping the standards that will define next generation modules for use in AI data centers, driving the future of innovation in infrastructure and performance,” said Mian Quddus, chairman, board of directors, JEDEC.