STMicroelectronics Assigned Five Patents

NVM device and corresponding method of operation
STMicroelectronics S.r.l., Agrate Brianza, Italy, and STMIcroelectronics (ALPS) SAS, Grenoble, France, has been assigned a patent (12494249) developed by Conte; Antonino, Tremestieri Etneo, Italy, Maccarrone; Agatino Massimo, Regalbuto, Italy, Tomaiuolo; Francesco, Acireale, Italy, Jouanneau; Thomas, Saint-Égrève, France, and Russo; Vincenzo, S. Maria di Licodia, Italy, for “non-volatile memory device and corresponding method of operation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In a non-volatile memory device, a memory sector is provided. The memory sector includes a plurality of tiles arranged horizontally. Each tile includes a plurality of memory cells arranged in horizontal word lines and vertical bit lines. A pre-decoder is configured to receive a set of encoded address signals to produce pre-decoding signals. A central row decoder is arranged in line with the plurality of tiles, receives the pre-decoding signals and produces level-shifted pull-up and pull-down driving signals for driving the word lines. First buffer circuits are arranged on a first side of each tile. Each of the first buffer circuits is coupled to a respective word line, receives a level-shifted pull-up driving signal and a level-shifted pull-down driving signal, and selectively pulls up or pulls down the respective word line as a function of the values of the received signals.”

The patent application was filed on 2023-09-08 (18/464093).

NVM with access control circuit for secure boot of electronic device
STMicroelectronics (Grand Ouest) SAS, Le Mans, France, has been assigned a patent (12488112) developed by Berthelot; Vincent, Saint Pavace, France, for a “non-volatile memory with access control circuit for secure boot of an electronic device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In an embodiment a method includes executing, during a first phase, one or more first codes stored in a first immutable zone of a non-volatile memory of an electronic device, forbidding, by an access control circuit of the non-volatile memory, execution of any codes stored in a second zone of the non-volatile memory during the first phase, executing, during a second phase, one or more second codes stored in the second zone and forbidding, by the access control circuit, any access to the first zone during the second phase.”

The patent application was filed on 2023-05-19 (18/320731).

Non-volatile phase-change memory device including distributed row decoder with n-channel MOSFET Transistors and related row decoding method
STMicroelectronics S.r.l., Agrate Brianza, Italy, and STMicroelectronics (Grenoble 2) SAS, Grenoble, France, has been assigned a patent (12482521) developed by Conte; Antonino, Tremestieri Etneo, Italy, Razafindraibe; Alin, Saint Martin d’Hères, France, Tomaiuolo; Francesco, Acireale, Italy, and Mortier; Thibault, Grenoble, France, for “non-volatile phase-change memory device including a distributed row decoder with n-channel MOSFET Transistors and related row decoding method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In an embodiment, a non-volatile memory device is proposed. The device includes a plurality of local pull-up stages distributed along a group of memory portions in a memory array. Each local pull-up stage includes, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type. The local pull-up transistors of each local pull-up are configured to locally decouple the corresponding wordline from a node at a first reference potential in response to a wordline that extends through the group of memory portions being selected, and locally couple the corresponding wordline to the node at the first reference potential in response to all the wordlines that extend through the group of memory portions being deselected to restore locally a deselection voltage on a wordline previously selected.”

The patent application was filed on 2024-01-06 (18/406097).

Memory cell with contiguous P-well and N-well structures
STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (12446218) developed by Bregoli; Roberto, Offlaga, Italy, Ferretti; Alessandro, Villanuova Sul Clisi, Italy, and Rosa; Federica, Corsico, Italy, for a “memory cell with contiguous P-well and N-well structures.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory cell includes a first well of a first conductivity type and a second well of a second conductivity type in a body adjacent to each other; a first conduction region, a second conduction region and a third conduction region in the first well, the first, second and third conduction regions being of the second conductivity type; a control gate region, of the first or second conductivity type, in the second well; a selection gate over the first well forming, together with the first and second conduction regions, a selection transistor; and a floating gate region. The floating gate region has a programming portion overlying the first well and a capacitive portion overlying the second well. The floating gate region forms, together with the second and third conduction regions, a storage transistor and, together with the control gate region, a capacitive element.”

The patent application was filed on 2023-03-17 (18/185575).

Flash memory device
STMicroelectronics (ALPS) SAS, Grenoble, France, has been assigned a patent (12443548) developed by Benhammadi; Jawad, Pont de Claix, France, for a “flash memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A FLASH memory device includes a FLASH memory having an array of non-volatile memory cells and a volatile memory. A FLASH memory interface is arranged outside of the FLASH memory, and a first communication bus couples the FLASH memory interface to the array of memory cells. A second communication bus couples the FLASH memory interface to the volatile memory.”

The patent application was filed on 2023-08-03 (18/365031).