R&D: NVM Non-Idealities Mitigation Solution Using Cell-Clustered Calibration for Analog High-Density Edge Multi-Level Cell Compute-in-Memory

IEEE Transactions on Circuits and Systems I: Regular Papers has published an article written by Zimeng Xu, Key Laboratory of Advanced Sensor and Integrated System, Tsinghua Shenzhen International Graduate School, Tsinghua University, Shenzhen, China, and Department of Electronic Engineering, LFET/BNRist/SKLSNC, Tsinghua University, Beijing, China, Taixin Li, Department of Electronic Engineering, LFET/BNRist/SKLSNC, Tsinghua University, Beijing, China, Ming-Yen Lee, Department of Electronic Engineering, Tsinghua University, Beijing, China, and School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA, Chenxi Jia, Department of Electronic Engineering, LFET/BNRist/SKLSNC, Tsinghua University, Beijing, China, Sheng Zhang, Key Laboratory of Advanced Sensor and Integrated System, Tsinghua Shenzhen International Graduate School, Tsinghua University, Shenzhen, China, Sumitha George, Department of ECE, North Dakota State University, Fargo, ND, USA, Huazhong Yang, Department of Electronic Engineering, LFET/BNRist/SKLSNC, Tsinghua University, Beijing, China, Vijaykrishnan Narayanan, Department of Computer Science and Engineering, The Pennsylvania State University, University Park, PA, USA, and Xueqing Li, Department of Electronic Engineering, LFET/BNRist/SKLSNC, Tsinghua University, Beijing, China.

Abstract: “Multi-level cell (MLC) non-volatile memory (NVM) has become a promising candidate for compute-in-memory (CiM) designs because of its non-volatility, high density, and improving CMOS compatibility. However, most MLC NVMs suffer from device non-idealities, including large variation, low on/off ratio, and read disturb, which compromise the computational accuracy, reliability, and throughput of MLC NVM-based CiMs. To alleviate the impact of these non-idealities, this work proposes a comprehensive mitigation solution, providing a new paradigm for achieving high-density MLC NVM-based CiM. Without loss of generality, MLC RRAM and STT-MRAM are taken as examples for design and evaluation in this paper. The highlight of the solution is the proposed cell-clustered computing paradigm with local recovery units (LRUs), which enables highly reliable local calibration and efficient in-memory computing. Besides, a dynamic boundary adaption technique is explored to restore the accuracy loss due to the RRAM state drift, and a segmented adaptive LRU configuration approach is proposed to improve the variation and temperature resilience of the MRAM-based design. Results show that the RRAM-based design achieves 152.3TOPS/W energy efficiency and improves the compute and storage density by 37.0\times and 131.3\times with 91.4% inference accuracy under 20% variation compared with the state-of-the-art (SOTA) MLC RRAM-CiM using on-chip write-and-verify. The MRAM counterpart achieves 182.0TOPS/W energy efficiency, 2.7\times compute density, 253.6\times storage density and 91.5% inference accuracy under 4% variation compared with the SOTA differential offset cancellation MLC MRAM-CiM. The performance reveals the significantly improved balance of the proposed MLC CiM between efficiency, density, and accuracy.“