R&D: Highly Efficient Built-In Self-Repair Techniques for NAND Flash Memory With Fine-Grained Redundancies

IEEE Access has published an article written by Shyue-Kung Lu, Shih-Chun Tseng, Department of Electrical Engineering, Dependable and Secure Computing (DSC) Laboratory, National Taiwan University of Science and Technology, Taipei, Taiwan, and Kohei Miyase, Department of Computer Science and Networks, Kyushu Institute of Technology, Iizuka, Japan.

Abstract: “Owing to the inherent architecture of NAND flash memory, the widely used redundant mechanisms for replacing faulty cells are limited to spare blocks and spare columns. Since the number of cells in a block and a column is typically very high, the efficiency of spare usage is consequently low. To address this issue and enhance the yield and reliability of flash memory, this paper proposes a novel fine-grained Built-In Self-Repair (BISR) technique. In addition to the basic read, program, and erase operations of flash memory cells, we also investigate their pass operations using the proposed March-CFT test algorithm. By analyzing the passability of faulty cells, conventional flash memory fault models can be further categorized into more precise repairable fault types (RTFs), including bit-, page-, column-, and NAND block-repairable fault types. Based on the proposed RFTs, the fine-grained BISR (FGBISR) can perform fault replacement using fine-grained spares, significantly improving repair efficiency. We also develop an efficient redundancy analysis algorithm suitable for Very Large Scale Integration (VLSI) implementation, along with the corresponding hardware architecture for FGBISR. A simulator is developed to evaluate repair rates, yield, reliability, and hardware overhead. Experimental results demonstrate that we can achieve substantial improvements with nearly negligible hardware overhead.“