OCP Global Summit 2025: Astera Labs Showcases Rack-Scale AI Ecosystem Momentum

Astera Labs, Inc., developer in semiconductor-based connectivity solutions for rack-scale AI infrastructure, announced from the 2025 OCP Global Summit comprehensive ecosystem collaborations that demonstrate growing industry momentum around open standards for AI Infrastructure 2.0-where entire racks function as unified computing platforms rather than collections of individual servers.Through live demonstrations and technical sessions, Astera Labs will showcase the breadth of support for solutions built with PCIe, UALink, Ethernet, CXL, and OpenBMC standards.

“The AI infrastructure landscape is rapidly evolving from server-level architectures to rack-scale systems operating as unified compute platforms,” said Patrick Moorhead, CEO and chief analyst, Moor Insights & Strategy. “As hyperscalers invest billions in next-gen infrastructure, open standards are critical to providing the flexibility needed to integrate diverse accelerators, interconnects, rack designs, and management tools-enabling fully optimized solutions for specialized AI workloads.”

These ecosystem collaborations are building momentum across key areas of rack-scale deployments:

• GPU and CPU connectivity for optimal compute performance
• Advanced cabling and connector solutions for robust signal integrity
• ODM manufacturing expertise for scalable deployment
• Intelligent management solutions for operational efficiency
• Comprehensive design enablement tools for faster market adoption

“Our approach to realizing AI Infrastructure 2.0 is simple: collaborate, standardize, and accelerate. Because when the ecosystem works together, innovation happens faster,” said Sanjay Gajendra, president and chief operating officer, Astera Labs. “Whether it’s GPU interoperability, manufacturing expertise, or rack-scale management-we are delivering intelligent connectivity for the AI workloads of today and tomorrow.”

At OCP Global Summit 2025, Astera Labs’ technical experts are presenting six sessions covering topics including UALink deployment strategies and PCIe 6 security considerations, while live demos at Booth #B33 highlight rack-scale AI connectivity solutions. Visit www.asteralabs.com/about/events/ocp2025 for the complete schedule or stop by Booth #B33 to experience these innovations firsthand.

Ecosystem Support
“The future of AI infrastructure depends on an open ecosystem that enables customers to choose the best AI accelerator for their specific workloads. Our collaboration with Astera Labs on UALink connectivity ensures our joint customers can deploy AMD Instinct GPUs at scale in open rack architectures that deliver performance, energy efficiency and flexibility,” said Danny Moore, director, AI technology and ecosystems, AMD.

“Designing and manufacturing high-performance cables for AI infrastructure requires deep collaboration with silicon connectivity providers. Our relationship with Astera Labs will ensure customers have access to reliable, high-speed cable solutions that extend Astera Labs’ connectivity capabilities from board-level to rack-scale deployments with supply chain diversity,” said Mark St. Hilaire, GM, high speed cables, Amphenol.

“AI infrastructure is rapidly evolving into tightly integrated systems that demand accelerated performance, power efficiency, and design flexibility. Our collaboration with Astera Labs is helping hyperscalers boost performance of AI systems with Neoverse-based CPUs and GPUs via high-bandwidth scale up connectivity solutions,” said Mohamed Awad, SVP and GM, infrastructure business, Arm.

“In collaboration with Astera Labs, we’ll be delivering a standards-based management and monitoring stack on OCP hardware that hyperscalers can seamlessly integrate into monitoring systems, extend across fleet orchestration layers, and leverage to maximize ROI from AI infrastructure. This relationship demonstrates our commitment to an open, interoperable ecosystem that accelerates deployment and ensures reliability at rack-scale,” said Chris Lin, chairman and president, Aspeed.

“When you’re pushing signals at PCIe 6 speeds across a rack full of different vendors’ chips, the analog design becomes absolutely critical – one poorly designed power rail or signal path can cripple performance for the entire system. Our collaboration with Astera Labs gives engineers the analog simulation and verification tools to get these high-speed connections right the first time, because at rack scale, there’s no room for signal integrity surprises,” said Ashutosh Mauskar, VP, product management, custom systems design and analysis products, Cadence Design Systems.

“Advanced optical connectivity becomes essential as AI infrastructure scales beyond traditional rack boundaries. Working with Astera Labs, we’ll integrate their connectivity intelligence with our advanced optical transceivers to deliver power-efficient, high-bandwidth solutions that maintain signal integrity across the extended distances required for modern AI data center architectures,” said Sean Davies, VP, sales, Eoptolink.

“Hyperscalers must accelerate time-to-market to keep pace with rapidly expanding scale and capacity demands of new AI models. Our global AI server manufacturing and rack-scale integration capabilities accelerate next-gen AI computing solutions, and working with Astera Labs, we deliver integrated connectivity support that addresses customers’ scale, performance, and time-to-market requirements,” said Ingrasys.

“OpenBMC has emerged as the de facto standard for platform management, and our collaboration with Astera Labs extends this proven framework to next-gen connectivity fabrics. By enabling standardized API support for retimers and scale-up switches, we will empower our mutual customers to accelerate AI infrastructure deployments with confidence-knowing their management and monitoring stack is rooted in open standards, validated at hyperscale, and ready for the future,” said Jeffrey Wang, president, Insyde Software.

“By working closely with Astera Labs, we’re optimizing cable and connector solutions for the latest standards like PCIe 6 and UALink 1.0 supporting 200G. Our complementary technologies work together to ensure robust signal integrity across rack-scale distances. This approach delivers high-value connectivity solutions while providing the supply chain diversity that enables customer flexibility in large-scale deployments,” said Chad Jameson, GM, IO solutions, Molex.

“Rack-scale AI infrastructure demands manufacturing precision and supply chain reliability that can only be achieved through close ecosystem partnerships. Our collaboration with Astera Labs ensures that customers receive validated, production-ready solutions that meet the demanding requirements of modern AI workloads,” said Mike Yang, EVP and president, QCT.

“Synopsys has a strong track record of delivering robust, silicon-proven IP and verification tools that enable industry leaders developing next-gen SoCs to adopt emerging interface standards with seamless interoperability across the ecosystem. Our collaboration with Astera Labs brings essential technologies to the ecosystem, accelerating the adoption of open rack architectures and enabling customers to achieve performance, interoperability, and scalability at rack scale,” said Neeraj Paliwal, SVP, IP product management, Synopsys.

“Our collaboration with Astera Labs extends beyond traditional cable assemblies to integrated backplane solutions that embed Aries retimer technology directly into the rack infrastructure. By incorporating Astera Labs’ intelligent retimers into our active backplane designs, we’re delivering increased density and reliable rack-scale connectivity while maintaining the high-speed performance for demanding AI workloads,” said Pranav Garg, VP, strategy, business development and marketing, digital data networks business unit, TE Connectivity.

“Innovation in AI system design requires close collaboration between connectivity providers and system manufacturers. Working with Astera Labs, Wistron is committed to delivering excellent and reliable manufactured products for hyperscale deployments,” said Pen Wei Wu, VP, enterprise & networking business group, Wistron.

“Next-gen AI demands rack-level integration that unifies connectivity and performance across systems. Our collaboration with Astera Labs delivers high-density rack architectures that maximize connectivity efficiency, enabling hyperscale customers to operate the entire rack as a single high-performance computing unit,” said Steven Hsieh, VP, Wiwynn.