R&D: Pushing Limits of NAND Technology Scaling with Ferroelectrics

MRS Bulletin has published an article written by Prasanna Venkatesan, Lance Fernandes, Sanghyun Kang, Priyankka Ravikumar, Taeyoung Song, Chinsung Park, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA, Dipjyoti Das, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA, and Department of Electronics and Communication Engineering, National Institute of Technology Silchar, Silchar, Assam, India, Kijoon H. P. Kim, Kwangyou Seo, Kwangsoo Kim, Samsung Electronics, Seoul, South Korea, Kai Ni, Department of Electrical Engineering, University of Notre Dame, Notre Dame, USA, Andrea Padovani, Department of Engineering “Enzo Ferrari”, UNIMORE, Modena, Italy, Mahendra Pakala, Luca Larcher, Gaurav Thareja, Applied Materials, Santa Clara, USA, Wanki Kim, Daewon Ha, Samsung Electronics, Seoul, South Korea,and Asif Khan, School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, USA, and School of Materials Science and Engineering, Georgia Institute of Technology, Atlanta, USA.

Abstract: “Artificial intelligence (AI) continues to drive transformative advancements across various industries. The data-intensive nature of AI training (and inferencing) has resulted in the generation of unprecedented volumes of data with machine-generated content surpassing human-generated data by more than 100-fold in 2025. Efficiently managing this data influx necessitates advanced digital storage technologies. However, traditional NAND flash memory, which is critical for supporting data flows in AI systems—alongside high-bandwidth memory, for AI training—faces fundamental scaling limitations as it approaches the 1000-layer milestone, encompassing more than 40 trillion transistors. This article delves into the potential of hafnia-based ferroelectric materials as a breakthrough solution to these challenges. Recent advancements indicate that the intrinsic limitations of ferroelectric field-effect transistors (FEFETs) can be mitigated through material and device-level engineering. These advancements enable FEFETs to meet the stringent density, reliability, and scalability requirements of future three-dimensional NAND technology. The role of ferroelectrics in addressing NAND scaling challenges and expanding storage capabilities presents a promising avenue for meeting the storage demands of the AI-driven era.“