Intel NDTM US Assigned Fourteen Patents

Memory cell sensing circuit with adjusted bias from pre-boost operation
Intel NDTM US LLC, Santa Clara, CA, San Jose, CA, has been assigned a patent (12394492) developed by Rajwade; Shantanu R., Santa Clara, CA, Nasri; Bayan, Folsom, CA, Fang; Tzu-Ning, Palo Alto, CA, Haque; Rezaul, Folsom, CA, Kulkarni; Dhanashree R., El Dorado Hills, CA, Ramanan; Narayanan, San Jose, CA, Amani; Matin, Fremont, CA, Rahman; Ahsanur, Folsom, CA, Park; Seong Je, San Jose, CA, and Mahuli; Netra, Folsom, CA, for a “memory cell sensing circuit with adjusted bias from pre-boost operation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A sense circuit performs a multistage boost, including a boost during precharge operation and a boost during the standard boost operation. The sense circuit includes an output transistor to drive a sense output based on current through a sense node which drives a gate of the output transistor. The sense circuit includes a precharge circuit to precharge the sense node and the gate of the output transistor and a boost circuit to boost the sense node. The boost circuit can be boosted during precharge by a first boost voltage, resulting in a lower boost applied to the sense node after precharge. The boost circuit boosts up the sense node by a second boost voltage lower than the first boost voltage. The boost circuit boosts the sense node down by the full boost voltage of the first boost voltage plus the second boost voltage after sensing.”

The patent application was filed on 2020-11-30 (17/107679).

Lean command sequence for multi-plane read operations
Intel NDTM US LLC, Santa Clara, CA, San Jose, CA, has been assigned a patent (12393367) developed by Vittal Prabhu; Naveen, Madraswala; Aliasgar, Rasoori; Sandeep, Folsom, CA, and Bemalkhedkar; Trupti, San Jose, CA, for a “lean command sequence for multi-plane read operations.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems, apparatuses and methods may provide for technology that generates address information for a plurality of planes in NAND memory, excludes column information from the address information, and sends a read command sequence to the NAND memory, wherein the read command sequence includes the address information. In one example, the technology also excludes plane confirm commands and busy cycles from the read command sequence.”

The patent application was filed on 2021-08-25 (17/411899).

Efficient bitline stabilization for program inhibit in NAND arrays
Intel NDTM US LLC, Santa Clara, CA, San Jose, CA, has been assigned a patent (12394497) developed by Ameen Beshari; Tarek Ahmed, San Jose, CA, Rajwade; Shantanu R., San Mateo, CA, Rahman; Ahsanur, Upadhyay; Sagar, and Chandrapati; Pratyush, Folsom, CA, for an “efficient bitline stabilization for program inhibit in NAND arrays.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A storage device charges bitlines in preparation for a program pulse. To charge the bitlines, the storage device connects the bitlines to an external regulator instead of an internal regulator to prepare them for the program pulse. The system can charge all bitlines to the external regulator high voltage reference before changing to the internal regulator for bitline stabilization before the program pulse.”

The patent application was filed on 2023-12-23 (18/395541).

Zero voltage program state detection
Intel NDTM US LLC, Santa Clara, CA, San Jose, CA, has been assigned a patent (12379989) developed by Gaewsky; Kristopher H., El Dorado Hills, CA, and Liou; Kevin K., Rancho Cordova, CA, for a “zero voltage program state detection.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “For NAND devices having a zero voltage program state as a result of a preconditioning operation, detecting the status of the zero voltage program state is important for customers to quickly validate their component and SSD flows to improve NAND retention and reliability after assembly and die level re-work. A zero voltage program state detection operation quickly determines the validity of the zero voltage program state of a NAND page of a NAND device. The detection operation includes reading a NAND page with reference voltages that delimit a predetermined acceptable range of voltage levels below and above a zero threshold voltage. If NAND memory cells having threshold voltage levels that fall below or above the acceptable voltage levels exceed a predetermined failed bytes limit for the NAND page, the zero voltage program state is invalid.”

The patent application was filed on 2023-03-20 (18/123946).

Read latency reduction for partially-programmed block of non-volatile memory
Intel NDTM US LLC, Santa Clara, CA, San Jose, CA, has been assigned a patent (12362016) developed by Doller; Joseph F., Gaewsky; Kristopher H., El Dorado Hills, CA, and Mebane; Noah, Sacramento, CA, for a “read latency reduction for partially-programmed block of non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Proactively adjusting read voltages at the system level, before performing a read operation on data located in a partially-programmed block in a block-addressable non-volatile memory, can significantly reduce the re-read trigger rate. This reduces the rate of entering a read recovery flow and subsequent read latency. Determining in advance a wordline-specific pattern of wordline offsets associated with past unsuccessful reads in partially-programmed blocks allows read voltages to be proactively adjusted for vulnerable wordlines. Read voltages are restored for subsequent read operations.”

The patent application was filed on 2020-12-04 (17/112401).

Staggered read recovery for improved read window budget in 3D NAND memory array
Intel NDTM US LLC, Santa Clara, CA, San Jose, CA, has been assigned a patent (12362002) developed by Ferdous; Rifat, Lafayette, IN, Kang; Sung-Taeg, Palo Alto, CA, Shenoy; Rohit S., Fremont, CA, Khakifirooz; Ali, Brookline, MA, and Basu; Dipanjan, Portland, OR, for a “staggered read recovery for improved read window budget in a three dimensional (3D) NAND memory array.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “At the end of or after a reading operation in a 3D (three dimensional) NAND array, the wordlines of the 3D NAND array can be transitioned to ground in a staggered manner. The 3D NAND array includes a 3D stack with multiple wordlines vertically stacked, including a bottom-most wordline, a top-most wordline, and middle wordlines between the bottom-most wordline and the top-most wordline. A controller that controls the reading can set the multiple wordlines to a high voltage at the end or after the reading operation and then transition a selected wordline of the multiple wordlines from the high voltage to ground prior to transitioning the other wordlines to ground. Thus, the controller will transition the other wordlines from the high voltage to ground after a delay.”

The patent application was filed on 2021-05-174 (17/322724).

Method and apparatus to reduce memory in NAND flash device to store page related information
Intel NDTM US LLC, Santa Clara, CA, San Jose, CA, has been assigned a patent (12360669) developed by Madraswala; Aliasgar S., Folsom, CA, Mookiah; Shanmathi, Santa Clara, CA, Chandrapati; Pratyush, and Vittal Prabhu; Naveen Prabhu, Folsom, CA, for “method and apparatus to reduce memory in a NAND flash device to store page related information.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The size of page map memory in a NAND flash device used to store page related information is decreased by embedding page type in a row address. The row address is received by the NAND flash device from the host on the data bus in a six-cycle sequence. The received row address is used to decode a physical page address received during the row address cycle to obtain a word line and a block segment number for a block segment in the word line in the NAND flash array. A same block segment number is used for each page type in the block segment.”

The patent application was filed on 2023-02-09 (18/107677).

Program verify process having placement aware pre-program verify (PPV) bucket size modulation
Intel NDTM US LLC, Santa Clara, CA, San Jose, CA, has been assigned a patent (12322455) developed by Rajwade; Shantanu R., Ameen Beshari; Tarek Ahmed, Santa Clara, CA, Amani; Matin, Fremont, CA, Ramanan; Narayanan, San Jose, CA, and Thathachary; Arun, Santa Clara, CA, for a “program verify process having placement aware pre-program verify (PPV) bucket size modulation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An apparatus is described. An apparatus includes controller logic circuitry to perform a program-verify programming process to a flash memory chip. The program-verify programming process is to reduce a size of a pre-program verify (PPV) bucket in response to a number of cells being fully programmed to a same digital state. The number of cells are less than a total number of cells to be programmed to the same digital state.”

The patent application was filed on 2021-05-14 (17/321114).

Grouped global wordline driver with shared bias scheme
Intel NDTM US LLC, Santa Clara, CA, San Jose, CA, has been assigned a patent (12315567) developed by Ha; Chang Wan, San Ramon, CA, Ngo; Binh, Rahman; Ahsanur, Chinnammagari; Radhika, and Upadhyay; Sagar, Folsom, CA, for a “grouped global wordline driver with shared bias scheme.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems, apparatuses, and methods may provide for technology that groups a plurality of wordline drivers together and supports these grouped wordline drivers via a shared multiplexer, a shared level shifter, and/or one or more shared multi-well level shifters. In one example, such technology includes a shared multiplexer and a first and second grouped global wordline driver coupled to the shared multiplexer. The shared multiplexer is to access data state information from a plurality of memory cells. The first grouped global wordline driver is to output a first plurality of wordlines associated with a first plane. The second grouped global wordline driver is to output a second plurality of wordlines associated with a second plane, where the second plane is different than the first plane.”

The patent application was filed on 2021-09-15 (17/475880).

Method and apparatus to reduce power consumption of page buffer circuitry in non-volatile memory device
Intel NDTM US LLC, Santa Clara, CA, San Jose, CA, has been assigned a patent (12315573) developed by Cichocki; Mattia, Rome, Italy, Moschiano; Violante, Avezzano, Italy, Vali; Tommaso, Sezze, Italy, Rizzo; Guido Luciano, Albignasego, Italy, Ha; Chang Wan, San Ramon, CA, and Fastow; Richard, Cupertino, CA, for “method and apparatus to reduce power consumption of page buffer circuitry in a non-volatile memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Power consumption of sensing circuitry in a NAND Flash device is reduced by reducing the voltage supply to a portion of logic circuits in sensing circuitry. A first power domain provides power to a first portion of the logic circuits in the sensing circuity and a second power domain provides power to a second portion of the logic circuits in the sensing circuitry. The first power domain has a higher voltage than the second power domain.”

The patent application was filed on 2023-03-28 (18/127217).

NAND sensing circuit and technique for read-disturb mitigation
Intel NDTM US LLC, Santa Clara, CA, San Jose, CA, has been assigned a patent (12266406) developed by Ramanan; Narayanan, San Jose, CA, for “NAND sensing circuit and technique for read-disturb mitigation.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Sensing circuits and techniques for NAND memory that can enable improved read disturb on the selected SGS are described herein. In one example, a reverse sensing circuit includes circuitry coupled with a bitline of the string of NAND memory cells to perform a sensing operation. The circuitry charges the bitline of the string of NAND memory cells to a target bitline voltage and applies a voltage to the source line that is higher than the bitline voltage. The sense current flows through the string from the source line to the bitline. The voltage at a sensing node that is indicative of a threshold voltage of a memory cell can then be detected.”

The patent application was filed on 2021-03-15 (17/202133).

Dynamic detection and dynamic adjustment of sub-threshold swing in memory cell sensing circuit
Intel NDTM US LLC, Santa Clara, CA, San Jose, CA, has been assigned a patent (12237023) developed by Ameen Beshari; Tarek Ahmed, Rajwade; Shantanu R., Santa Clara, CA, Amani; Matin, Fremont, CA, and Ramanan; Narayanan, San Jose, CA, for “dynamic detection and dynamic adjustment of sub-threshold swing in a memory cell sensing circuit.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “For a nonvolatile (NV) storage media such as NAND media that is written by a program and program verify operation, the system can determine an expected number of SSPC (selective slow programming convergence) cells for a page of cells for specific conditions of the page. The system can perform program verify with a first wordline (WL) select voltage for SSPC cell detection for a first write of the page to detect the expected number of SSPC cells. Based on the determined expected number of SSPC cells, the system can set a boost voltage to capture an expected number of SSPC cells during the program verify operation. The system performs program verify for subsequent writes to the page with a higher WL select voltage, to perform program verify for standard cells and then SSPC program verify with the boost voltage determined from the first write.”

The patent application was filed on 2020-12-24 (17/134010).

Dynamic program caching
Intel NDTM US LLC, Santa Clara, CA, San Jose, CA, has been assigned a patent (12230334) developed by Madraswala; Aliasgar S., Folsom, CA, Khakifirooz; Ali, Brookline, MA, Venkataramaiah; Bhaskar, Upadhyay; Sagar, and Wakchaure; Yogesh B., Folsom, CA, for a “dynamic program caching.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Dynamic program caching reduces latency of a program operation on multi-level cell (MLC) memory having at least three pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND. A controller determines that the program operation can be initiated without loading all pages into the memory. In response, the NAND loads a first page and then executes portions of the program operation in parallel, at least in part, with loading subsequent pages. The NAND behavior is modified to monitor data loading completion times, to copy pages from a cache register to a data register as needed, and to resume program operation if a shutdown occurs. The portions of the program operation include a program prologue operation and a pulse verify loop for the first voltage level (L1) of the MLC memory.”

The patent application was filed on 2022-03-31 (17/710978).

Skip program verify for dynamic start voltage sampling
Intel NDTM US LLC, Santa Clara, CA, San Jose, CA, has been assigned a patent (12189955) developed by Tankasala; Archana, Sunnyvale, CA, Upadhyay; Sagar, Folsom, CA, Rajwade; Shantanu R., San Mateo, CA, and Madraswala; Aliasgar S., Folsom, CA, for a “skip program verify for dynamic start voltage sampling.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Skip program verify for dynamic start voltage (DSV) sampling reduces latency of a program operation on multi-level cell (MLC) memory having at least two pages and programmable with multiple threshold voltage levels, such as a Triple Level Cell (TLC) NAND device. The NAND device skips program verifies corresponding to higher levels of voltage thresholds during DSV sampling. As a result, the NAND device can reduce a total program time (tPROG) to program the MLC memory, and determine the dynamic start program voltage more quickly. The NAND device can improve an effective TLC NAND tPROG by as much as 2% without impacting the placement of the first sub-block being programmed. The skipped program verifies corresponding to the higher levels of voltage thresholds are resumed as soon as DSV sampling is complete.”

The patent application was filed on 2022-12-28 (18/089969).