R&D: Middle Interlayer Engineered Ferroelectric NAND Flash Overcoming Reliability and Stability Bottlenecks for Next-Gen High-Density Storage Systems

Advanced Science has published an article written by Giuk Kim, Sangho Lee, Hyojun Choi, Yangjin Jung, Woongjin Kim, Department of Electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141 South Korea, Sanghyun Park, Kwangyou Seo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Semiconductor R&D Center, Samsung Electronics, Hwaseong-si, 18367 South Korea, Mincheol Shin, Department of Electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141 South Korea, Jinho Ahn, Department of Material Science Engineering, Hanyang University, Seoul, 04763 South Korea, and Sanghun Jeon, Department of Electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141 South Korea.

Abstract: “Multilevel storage and low-voltage operation position ferroelectric transistors as promising candidates for next-generation nonvolatile memory. Among them, gate-injection-type ferroelectric transistors offer improved vertical scalability and power efficiency for three-dimensional (3D) NAND flash. However, their intricate interplay between polarization switching and charge trapping complicates systematic understanding of degradation mechanisms, limiting strategies to improve reliability and stability. Here, gate stack engineering incorporating middle interlayers within HfZrO_x matrix is presented to modulate polarization dynamics, strengthening the coupling of dual mechanisms and overcoming long-standing reliability and stability bottlenecks in ferroelectric NAND operation. This approach achieves a memory window up to 11 V, an operating voltage below 18 V, triple-level-cell retention beyond 10 years, disturbance immunity, and 54% reduced threshold voltage variability. A 20% reduction in program voltage compared to conventional NAND enables aggressive vertical scaling, leading to 25% higher bit-density. Furthermore, analytical modeling provides insights into gate stack optimization. These findings establish ferroelectric NAND as a scalable, energy-efficient solution for next-generation storage.“