R&D: Can Hardware Outsmart Software in Tiered Memory Management? – CMM-H Case Study

ACM Digital Library has published, in SYSTOR ’25: Proceedings of the 18th ACM International Systems and Storage Conference, an article written by Zhen Lin, Yujie Yang, Lingfeng Xiang, The University of Texas at Arlington, Arlington, Texas, USA, Lianjie Cao, Faraz Ahmed, Hewlett Packard Labs, Milpitas, California, USA, Jia Rao, Hui Lu, The University of Texas at Arlington, Arlington, Texas, USA, and Puneet Sharma, Hewlett Packard Labs, Milpitas, California, USA.

Abstract: “With the advent of Compute Express Link (CXL), hardware-managed memory tiering has become a reality. In this paper, we investigate Samsung’s CXL Memory Module-Hybrid (CMM-H), a CXL Type 3 device integrating DRAM and NAND flash managed by an FPGA-based controller and providing byte-addressable memory interface via the cxl.mem protocol. We perform a detailed evaluation of CMM-H and compare its performance with OS-level and block-level tiering solutions. Our results highlight the performance benefits of CMM-H for cache-hit scenarios and identify key limitations for cache-miss situations, offering insights into the trade-offs involved in adopting hardware-managed memory tiering in emerging CXL-based systems.“