R&D: Two Articles on Non-Volatile Memory Technologies

R&D: Driving for More Moore on Computing Devices with Advanced Non-Volatile Memory Technology

Improvements align with the broader vision of both “More Moore” and “More than Moore” – extending beyond MOS device miniaturization to encompass architectural and functional innovation that redefines how performance is achieved at the end of CMOS device downsizing.

Electronics has published an article written by Hei Wong, Department of Electrical Engineering, City University of Hong Kong, Hong Kong, China, Weidong Li, Yangtze Memory Technologies Co., Ltd., East Lake High-Tech Development Zone, Wuhan 430078, China, Jieqiong Zhang, Hubei Jiu Feng Shan Laboratory, Wuhan 430074, China, Wenhan Bao, Department of Electrical Engineering, City University of Hong Kong, Hong Kong, China, Lichao Wu, and Jun Liu, Hubei Jiu Feng Shan Laboratory, Wuhan 430074, China.

Abstract: “As the CMOS technology approaches its physical and economic limits, further advancement of Moore’s Law for enhanced computing performance can no longer rely solely on smaller transistors and higher integration density. Instead, the computing landscape is poised for a fundamental transformation that transcends hardware scaling to embrace innovations in architecture, software, application-specific algorithms, and cross-disciplinary integration. Among the most promising enablers of this transition is non-volatile memory (NVM), which provides new technological pathways for restructuring the future of computing systems. Recent advancements in non-volatile memory (NVM) technologies, such as flash memory, Resistive Random-Access Memory (RRAM), and magneto-resistive RAM (MRAM), have significantly narrowed longstanding performance gaps while introducing transformative capabilities, including instant-on functionality, ultra-low standby power, and persistent data retention. These characteristics pave the way for developing more energy-efficient computing systems, heterogeneous memory hierarchies, and novel computational paradigms, such as in-memory and neuromorphic computing. Beyond isolated hardware improvements, integrating NVM at both the architectural and algorithmic levels would foster the emergence of intelligent computing platforms that transcend the limitations of traditional von Neumann architectures and device scaling. Driven by these advances, next-generation computing platforms powered by NVM are expected to deliver substantial gains in computational performance, energy efficiency, and scalability of the emerging data-centric architectures. These improvements align with the broader vision of both “More Moore” and “More than Moore”—extending beyond MOS device miniaturization to encompass architectural and functional innovation that redefines how performance is achieved at the end of CMOS device downsizing.“

R&D: Cross-Layer Design and Design Automation for In-Memory Computing based on Non-Volatile Memory Technologies

Article reviews key advancements in simulation and design tools for IMC fabrics, with a focus on NVM-based crossbar arrays and content-addressable memories, while highlighting the necessity of cross-layer collaboration.

IEEE Design & Test has published an article written by X. Sharon Hu, University of Notre Dame, USA, Ming-Yen Lee, Georgia Institute of Technology, USA, Mengyuan Li, University of Notre Dame, USA, João Paulo Cardoso De Lima, TU Dresden and ScaDS.AI Dresden/Leipzig, Germany, Liu Liu; Zhenhua Zhu, Tsinghua University, China, Jeronimo Castrillon, TU Dresden and ScaDS.AI Dresden/Leipzig, Germany, Michael Niemier, University of Notre Dame, USA, and Yu Wang, Tsinghua University, China.

Abstract: “Data transfer between processors and memory remains a critical bottleneck in improving application performance on traditional computing hardware, particularly for data-intensive workloads such as machine learning, bioinformatics, and security applications. In-memory computing (IMC), a paradigm where a substantial portion of data processing occurs directly within memory, has emerged as a promising solution to mitigate this bottleneck. The advancement of emerging non-volatile memory (NVM) technologies has further accelerated the development of IMC hardware fabrics. However, harnessing the full potential of IMC requires a cross-layer design approach that spans memory technologies, circuits, architectures, and systems. Essential cross-layer tools—including modeling and simulation, data partitioning and mapping, and operation scheduling—play a pivotal role in designing efficient IMC-based hardware. This article reviews key advancements in simulation and design tools for IMC fabrics, with a focus on NVM-based crossbar arrays and content-addressable memories, while highlighting the necessity of cross-layer collaboration. Additionally, we discuss current challenges and emerging opportunities in the field.“