R&D: Three Articles on NAND Flash

R&D: Middle Interlayer Engineered Ferroelectric NAND Flash Overcoming Reliability and Stability Bottlenecks for Next-Gen High-Density Storage Systems

Findings establish ferroelectric NAND as scalable, energy-efficient solution for next-gen storage.

Advanced Science has published an article written by Giuk Kim, Sangho Lee, Hyojun Choi, Yangjin Jung, Woongjin Kim, Department of Electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141 South Korea, Sanghyun Park, Kwangyou Seo, Kwangsoo Kim, Wanki Kim, Daewon Ha, Semiconductor R&D Center, Samsung Electronics, Hwaseong-si, 18367 South Korea, Mincheol Shin, Department of Electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141 South Korea, Jinho Ahn, Department of Material Science Engineering, Hanyang University, Seoul, 04763 South Korea, and Sanghun Jeon, Department of Electrical engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, 34141 South Korea.

Abstract: “Multilevel storage and low-voltage operation position ferroelectric transistors as promising candidates for next-generation nonvolatile memory. Among them, gate-injection-type ferroelectric transistors offer improved vertical scalability and power efficiency for three-dimensional (3D) NAND flash. However, their intricate interplay between polarization switching and charge trapping complicates systematic understanding of degradation mechanisms, limiting strategies to improve reliability and stability. Here, gate stack engineering incorporating middle interlayers within HfZrO_x matrix is presented to modulate polarization dynamics, strengthening the coupling of dual mechanisms and overcoming long-standing reliability and stability bottlenecks in ferroelectric NAND operation. This approach achieves a memory window up to 11 V, an operating voltage below 18 V, triple-level-cell retention beyond 10 years, disturbance immunity, and 54% reduced threshold voltage variability. A 20% reduction in program voltage compared to conventional NAND enables aggressive vertical scaling, leading to 25% higher bit-density. Furthermore, analytical modeling provides insights into gate stack optimization. These findings establish ferroelectric NAND as a scalable, energy-efficient solution for next-generation storage.“

R&D: Modeling Attempt-to-Escape Frequency, Tunneling Emission of Trapped Electrons in Tunneling Oxides of 3D NAND Flash Memory

Authors propose novel physical model for the attempt-to-escape frequency of trap-to-band electron emission, which is broadly applicable to various trap-to-band scenarios.

IEEE Transactions on Electron Devices has published an article written by Myung Jin, Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea, and Hyungcheol Shin, Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea, and Integra Semiconductor, Ltd., Seoul, South Korea.

Abstract: “We propose a novel physical model for the attempt-to-escape frequency of trap-to-band electron emission, which is broadly applicable to various trap-to-band scenarios. The model is verified under detrapping mechanisms in bandgap-engineered tunneling oxide (BETOX), enabling accurate prediction of electron emission dynamics within extremely short timeframes. Extensive comparisons between the proposed model and calibrated TCAD simulations demonstrate excellent agreement, validating its accuracy and reliability. Additionally, based on calibrated physical parameters, the model is adaptable to engineering variations such as trap profiles, including intricate combinations of Gaussian trap distributions, making it highly versatile for future device optimization and analysis.“

R&D: Physical Unclonable Function With Enlarged String Current Variation in NAND Flash Array by WL Selection Scheme

Authors present a NAND flash-based physical unclonable function (PUF) system

IEEE Transactions on Electron Devices has published an article written by Dayeon Yu, Division of Materials Science and Engineering and the Department of Semiconductor Engineering, Hanyang University, Seoul, South Korea, Suhyeon Ahn, Department of Electrical and Computer Engineering, Inha University, Incheon, South Korea, Hwiho Hwang, and Hyungjin Kim, Division of Materials Science and Engineering and the Department of Semiconductor Engineering, Hanyang University, Seoul, South Korea.

Abstract: “In this work, we present a NAND flash-based physical unclonable function (PUF) system. This system utilizes the intrinsic device variations of NAND flash cells as an entropy source, effectively addressing the limited variation distribution inherent in conventional NAND flash due to its serially connected structure. We experimentally validated the enhancement in the randomness of the entropy source using a fabricated 32 × 32 NAND flash array. The variation in bitline current is analyzed as a function of the number of selected wordlines (N_WL), and a large variation is achieved by limiting N_WL. Based on the measured data, we confirm that the bit-error rate (BER) of the 3-D NAND flash based PUF system exhibits a negligible increase of just 0.073% per 10 ^∘C, demonstrating its high stability against temperature variation. Additionally, we evaluate the randomness metrics of the PUF system, such as uniformity, diffuseness, and uniqueness, by utilizing the challenge-response pair (CRP) space. The security of the PUF system is also assessed against machine learning (ML) attacks.“