R&D: Beyond Bandwidth Doubling, Embrace Bit-Flips and Unlock Processing-in-NAND

IEEE Xplore has published, in 2025 IEEE 41st International Conference on Data Engineering (ICDE) proceedings, an article written by Maximilian Berens, Yun-Chih Chen, TU Dortmund University, Dortmund, Germany, Jian-Jia Chen, and Jens Teubner, TU Dortmund University, Dortmund, Germany, and Lamarr Institute for Machine Learning and Artificial Intelligence, Dortmund, Germany.

Abstract: “NVMe SSDs offer unprecedented capacity and bandwidth and upcoming PCIe standards promise even more. However, the underlying technology, NAND memory, already struggles with significant heat and power consumption challenges. Just like microprocessors before, NAND also experiences Dark Silicon, preventing performance from improving at the same pace as capacity. Much of the power (and thus heat) within a NAND chip results from transferring data at a high rate, another symptom of a compute-centric style of processing. Therefore, we argue for data-centric Processing-in-NAND (PiN). However, PiN comes with significant challenges, such as limited capabilities and the need to cope with bit-flip errors. Even beyond Processing-in-Memory (PiM), databases may soon have to accept that memory is not error-free, an assumption that comes at a significant cost in power, capacity and performance. Our discussion indicates that no PiN design will serve as a singular, universally applicable solution to the limit of bandwidth scaling. Instead, successful integration into database architecture requires carefully identifying PiN-compatible functionality and abstractions, and cooperation with other innovations, such as Computational Storage and CXL. Lastly, we analyze the fundamental error tolerance of Bloom filters and binary sketches as PiM-compatible data structures, which we believe may be of independent interest.“