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Marvell CXL Ecosystem with Structera Interoperability Across all Major Memory and CPU Platforms

Proven interoperability and flexibility drives hyperscaler deployment of next-gen scalable infrastructure, successfully completed interoperability testing with DDR4 and DDR5 memory solutions from Micron, Samsung, and SK hynix

Marvell Technology, Inc. announced the Structera Compute Express Link (CXL) memory-expansion controllers and near memory compute accelerators have successfully completed interoperability testing with DDR4 and DDR5 memory solutions from Micron Technology, Inc., Samsung Electronics, and SK hynix, Inc

Marvell Structura Cxl Cxl EcosystemThis milestone follows the recent announcement Successful Interoperability of Structera CXL Portfolio with AMD EPYC CPU and 5th Gen Intel Xeon Scalable Platforms, making Structera the only CXL 2.0 product family with completed interoperability testing across both leading CPU architectures and all three major memory suppliers.

As data-centric applications grow in complexity and memory plays a greater role in performance, interoperability is critical. Validation of Structera with DDR4 and DDR5 enables scalable system design, reduces integration risk, and streamlines qualification, while giving OEMs and cloud providers the flexibility to optimize system designs while maintaining supply chain flexibility.

To meet hyperscalers’ demand for seamless integration across diverse memory and CPU technologies, Structera ensures compatibility and flexible configuration options that accelerate qualification and enable scalable deployment. A flexible business engagement model from Marvell enables innovative deployment strategies for Structera, allowing tailored product configurations that align with specific workload requirements and support both standard and custom deployment models.

To support diverse system architectures, Structera IP is available for integration into custom silicon designs. This allows customers to embed silicon-proven CXL technology from the companyl directly into their chips, unlocking new opportunities to optimize workload-specific performance, power efficiency, and system cost. The IP offering supports a broad range of integration models – from fully custom SoCs to tightly coupled accelerators – providing design flexibility while leveraging the mature CXL ecosystem and interoperability leadership developed by Marvell.

As AI and high-performance computing workloads intensify, CXL will help dissolve bottlenecks for demanding workloads that can consume upwards of hundreds of terabytes of memory capacity,” said Praveen Vaidyanathan, VP and GM, cloud memory products, Micron. “Our collaboration with Marvell to validate Structera with Micron’s memory technology is expected to deliver scalable, high-efficiency CXL infrastructure for the new frontier of AI.” 

CXL is reshaping how memory is deployed in data centers,” said Jangseok Choi, VP, Samsung Electronics. “Our work with Marvell ensures that customers can confidently deploy Structera with Samsung DDR memory for reliable, high-performance systems.”

Working with Marvell to validate Structera with SK hynix memory supports our shared goal of making memory expansion more accessible and flexible,” said Uksong Kang, head, next generation product planning and enabling, SK hynix. “This gives customers the tools they need to build future-ready architectures with less friction and more choice.” 

The Structera product line includes 2 CXL device families engineered to meet the diverse performance and scalability needs of next-gen cloud data centers. The Structera A CXL near-memory accelerators integrate 16 Arm Neoverse V2 cores and multiple memory channels with CXL to address high-bandwidth memory applications such as deep learning recommendation models (DLRM) and machine learning. The Structera X CXL memory-expansion controllers enable TBs of memory to be added to general-purpose servers and address high-capacity memory applications such as in-memory databases. The Structera CXL device families are the industry’s 1st to support 4 memory channels, integrate inline LZ4 compression and use 5nm manufacturing processes.

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