Faraday Delivers DDR/LPDDR Combo PHY IP Solutions on UMC’s 22ULP and 14FFC

Faraday Technology Corporation announced the availability of its DDR/LPDDR combo PHY, supporting from 3^rd to 5^th Gen on UMC’s 22ULP and 14FFC platforms, which are UMC’s planar and FinFET process technologies.

The company continues its long-standing commitment to delivering in-house IP solutions optimized to better serve the ASIC market.

The firm’s DDR/LPDDR IP solutions feature robust, silicon-proven designs widely adopted in ASIC projects across diverse SoC applications. Full compliance with JEDEC specifications ensures compatibility and allows for flexible performance and power optimization. The 22ULP PHY supports low operating voltage at 0.8V, making it for power-sensitive applications such as mobile, 5G, and IoT devices. The 14nm PHY supports transmission rate up to 6,400Mb/s for DDR5/LPDDR5 and includes advanced features such as self-training mechanisms, impedance calibration, and DFE.

“Our customers demand high performance and low power in increasingly complex SoCs,” said Flash Lin, COO, Faraday. “With the complete DDR/LPDDR IP solution spanning controller, PHY, and subsystem integration, we’re helping customers accelerate design cycles, reduce development risks, and deliver high-quality, reliable memory subsystems.”