R&D: Investigation of Random Telegraph Noise Scaling Dependency in 3D NAND Using Monte Carlo Simulator

IEEE Transactions on Electron Devices has published an article written by Eunseok Oh, Department of ECE and ISRC, Seoul National University, Seoul, South Korea, and Hyungcheol Shin, Department of ECE and ISRC, Seoul National University, Seoul, South Korea, and Integra Semiconductor Ltd, Seoul, South Korea.

Abstract: “Random telegraph noise (RTN) shifts the threshold voltage (V_t) of 3-D NAND flash memory cells, making it a major cause of device malfunction. As device scaling continues, RTN has become an increasingly significant factor affecting device performance. The aim of this study is to develop a simulator that predicts the distribution of V_t shifts induced by RTN in scaled 3-D NAND flash memory. Previous RTN analysis methods rely heavily on numerous simulations or measurements, which are not only time-consuming but also limited in predicting the effects of device scaling on RTN-induced V_t shifts. To address these limitations, we developed a novel RTN Monte Carlo simulator that integrates a previously developed artificial neural network (ANN)-based machine learning (ML) model with a Markov process for trap occupancy states. Using this simulator, we comprehensively analyzed RTN effects in 3-D NAND devices with multiple traps, extracted the corresponding decay constants (λ), and modeled the dependence of λ on device physical parameters. The simulator provides flexibility in generating large-scale RTN data without the need for additional simulations or measurements, significantly reducing computation time while maintaining accuracy.“