SK hynix NAND Product Solutions Assigned Eighteen Patents

Improving read command process times in SSDs by having processor split-up background writes based on determined command size
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12366962) developed by Golez; Mark Anthony Sumabat, Folsom, CA, Chu; Henry, Rancho Cordova, CA, Vishwanath; Darshan Mallapur, Santa Clara, CA, Gangadhar; Sarvesh Varakabe, San Jose, CA, and Pelster; David J., Longmont, CO, for a “system method for improving read command process times in solid-state drives (SSD) by having processor split-up background writes based on determined command size.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Mechanisms for improving read command processing times in a solid-state drive (SSD) are provided, the mechanisms comprising: determining a workload type of an SSD; in response to determining that the workload type is a pure read workload type: determining at least one command size into which an original background write is to be split-up using at least one hardware processor; and splitting-up the background write into a plurality of split background writes, each having one of the determined at least one command size. In some embodiments, the at least one command size accounts for a page of the physical medium of the SSD. In some embodiments, the at least one command size includes at least two different sizes. In some embodiments, the mechanisms further comprise combining two or more split background writes. In some embodiments, the original background write is split-up before being placed in a channel queue.”

The patent application was filed on 2022-12-28 (18/090358).

On-SSD-copy techniques using copy-on-write
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12366986) developed by Li; Peng, Beaverton, OR, Trika; Sanjeev N., Portland, OR, and Estrada; David C., Portland, OR, for “on-SSD-copy techniques using copy-on-write.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “On-SSD-copy using Copy-On-Write (COW) techniques track indirection updates to the copied data without duplicating the data. In one example, a method involves receiving a copy command to copy data from a source LBA to a destination LBA. An entry in a logical-to-physical (L2P) table corresponding to the destination LBA is updated to refer to the same physical address as the source LBA’s entry in the L2P table. Flags in the L2P table are updated to indicate that more than one LBA refers to the same physical address. After updating the L2P table and before copying the data, a token is stored to the storage device. After storing the token, but before copying the data, an acknowledgement can be sent to the host to indicate the copy command is complete. A subsequent write to either the source or destination LBAs trigger a copy of the data.”

The patent application was filed on 2021-03-16 (17/203174).

SSD with multiplexed internal channel access during program data transfers
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12366965) developed by Pelster; David J., Longmont, CO, Wakchaure; Yogesh B., Folsom, CA, Vemula; Neelesh, Sunnyvale, CA, Madraswala; Aliasgar S., Folsom, CA, Carlton; David B., Oakland, CA, Sebastian; Donia, Fair Oaks, CA, Golez; Mark Anthony, Folsom, CA, and Guo; Xin, San Jose, CA, for a “solid state drive with multiplexed internal channel access during program data transfers.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method performed by a solid state drive is described. The method includes, on a channel that internally couples a controller of the solid state drive to a storage device of the solid state drive, sending write data for a program operation to be performed by one of the storage device’s logical units in separate chunks over the channel. The method also includes inserting higher priority traffic items of other logical units of the storage device in between the separate chunks.”

The patent application was filed on 2023-09-27 (18/373480).

Interposer with step feature
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12347784) developed by Pon; Florence, and Xu; Yi, Folsom, CA, for an “interposer with step feature.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to an interposer with step features used to electrically couple stacked dies. In embodiments, the step features may appear as a ziggurat shape to one or more sides of the interposer, which may be referred to as a ziggurat interposer. The interposer may have electrical routing disposed within to electrically couple the first face of the one of the step features with a die.”

The patent application was filed on 2019-03-27 (16/365811).

Host controlled garbage collection in SSD
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12340113) developed by Dutta; Bishwajit, Hillsboro, OR, Ramalingam; Anand S., Trika; Sanjeev N., Portland, OR, and Gala; Pallav H., Hillsboro, OR, for a “host controlled garbage collection in a solid state drive.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Read Quality of Service in a solid state drive is improved by allowing a host system communicatively coupled to the solid state drive to control garbage collection in the solid state drive. Through the use of controlled garbage collection, the host system can control when to start and stop garbage collection in the solid state drive and the number of NAND dies engaged in garbage-collection operations.”

The patent application was filed on 2021-03-27 (17/214819).

Flash memory chip that modulates its program step voltage as function of chip temperature
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12340847) developed by Hazeghi; Arash, Kalavade; Pranav, San Jose, CA, Shenoy; Rohit S., Fremont, CA, and Hang; Hsiao-Yu, Sunnyvale, CA, for a “flash memory chip that modulates its program step voltage as a function of chip temperature.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A method is described. The method includes performing the following on a flash memory chip: measuring a temperature of the flash memory chip; and, changing a program step size voltage of the flash memory chip because the temperature of the flash memory chip has changed.”

The patent application was filed on 2024-01-02 (18/402572).

Split block array for 3D NAND memory
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12340845) developed by Ha; Chang Wan, San Ramon, CA, Thimmegowda; Deepak, Fremont, CA, Koh; Hoon, San Jose, CA, Gularte; Richard M., Santa Clara, CA, Liu; Liu, Dalian, China, Meyaard; David, Boise, ID, and Rahman; Ahsanur, Santa Clara, CA, for a “split block array for 3D NAND memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.”

The patent application was filed on 2021-06-09 (17/343584).

Media for prioritizing read accesses to storage devices
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12340118) developed by de Vries; Jonathan, Folsom, CA, and Vemula; Neelesh, Santa Clara, CA, for “systems, methods, and media for prioritizing read accesses to storage devices.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Mechanisms for prioritizing read commands over write commands to a storage device are provided, the mechanisms comprising: determining counts of read commands targeting a plurality of portions of the storage device; calculating a threshold based on a function of an average of the counts of read commands targeting the plurality of portions of the storage device; determining that a count of read command(s) targeting one of the plurality of portions of the storage device meets the threshold; and in response to determining that the count of read command(s) targeting the one of the plurality of portions of the storage device meets the threshold, prioritizing a read command to access the one of the plurality of portions of the storage device over at least one write command.”

The patent application was filed on 2022-10-31 (17/977975).

Check node updates in bit flipping decoders
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12341530) developed by Kwok; Zion, Burnaby, Canada, and Ji; Young Joon, Vancouver, Canada, for a “check node updates in bit flipping decoders.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “This application is directed to error correction for data stored in a memory device. In response to a request to validate a block of data, the memory device identifies a set of check nodes corresponding to a set of variable nodes that represent the block of data. First check node values of the check nodes are determined based on the block of data, and stored in first registers. The memory device implements a plurality of iterations of error correction by flipping a subset of variable nodes successively during each iteration; determining second check node values of the check nodes; and updating the first check node values stored in the first registers based on the second check node values once in each of a first set of iterations and successively with flipping of each variable node in a second set of iterations following the first set of iterations.”

The patent application was filed on 2023-12-20 (18/391223).

Independent multi-page read operation enhancement technology
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12334136) developed by Prabhu; Naveen Prabhu Vittal, Madraswala; Aliasgar S., Pathak; Bharat, Ngo; Binh, Mahuli; Netra, Folsom, CA, and Rahman; Ahsanur, Santa Clara, CA, for an “independent multi-page read operation enhancement technology.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems, apparatuses and methods may provide for technology that sends a first command to a NAND die, sends first address information to the NAND die, and sends a second command to the NAND die, wherein the first command and the second command define a first command sequence and wherein the first address information signal a beginning of a first asynchronous read request from a first plurality of planes. In one example, the technology also sends a second command sequence and second address information to the NAND die wherein the second command sequence signals an end of the first asynchronous read request.”

The patent application was filed on 2021-06-24 (17/357466).

Simultaneous programming of multiple sub-blocks in NAND memory structures
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12334152) developed by Khakifirooz; Ali, Brookline, MA, Kalavade; Pranav, San Jose, CA, Rajwade; Shantanu, and Ameen Beshari; Tarek Ahmed, Santa Clara, CA, for “simultaneous programming of multiple sub-blocks in NAND memory structures.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems, apparatuses and methods may provide for technology that boosts strings of a plurality of NAND sub-blocks to a pass voltage, deboosts a first subset of the boosted strings based on data associated with the plurality of NAND sub-blocks, and simultaneously programs the first subset while a second subset of the boosted strings remain at the pass voltage. In one example, to boost the strings of the NAND sub-blocks, the technology applies the pass voltage to selected and unselected wordlines that are connected to the NAND sub-blocks while selected and unselected strings are disconnected from a bitline that receives the data associated with the NAND sub-blocks.”

The patent application was filed on 2021-03-25 (17/212792).

Pump discharge sequence improvements in external power supply mode for pulse recovery phases in NVM
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12334158) developed by Park; Soo-yong, San Jose, CA, Chava; Pranav, and Ngo; Binh, Folsom, CA, for a “pump discharge sequence improvements in external power supply mode for pulse recovery phases in non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems, apparatuses and methods may provide for technology that includes a charge pump and applies a program voltage from the charge pump to selected wordlines in the NAND memory. The technology may also conduct a discharge of the program voltage from the charge pump and maintain a connection between the selected wordlines and a pass voltage of the charge pump while the program voltage is being discharged. In one example, the connection between the selected wordlines and the pass voltage prevents the selected wordlines from floating.”

The patent application was filed on 2021-12-08 (17/545672).

Operating low-density parity-check bit-flipping decoder
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12316345) developed by Kwok; Zion, Burnaby, Canada, for “systems and methods for operating low-density parity-check bit-flipping decoder.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Systems and methods for operating a low-density parity-check (LDPC) bit-flipping decoder are disclosed herein. An LDPC codeword is received, and each bit in the LDPC codeword is classified as either a high-confidence bit or a low-confidence bit based on at least one criterion. The LDPC codeword is iteratively processed over a plurality of iterations based on parity check equations associated with each bit of the LDPC codeword to generate a processed LDPC codeword. For each iteration of the plurality of iterations, the iterative processing includes flipping at least one bit of the LDPC codeword, while preventing, for a first n number of the plurality of iterations, bits classified as high-confidence bits from comprising more than 33% of the total number of flipped bits. The processed LDPC codeword is decoded.”

The patent application was filed on 2022-12-28 (18/089912).

Data storage system with parallel array of dense memory cards and high airflow
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12306681) developed by Nelson; Michael D., Mountain View, CA, Khan; Jawad B., Cornelius, OR, Webb; Randall K., Portland, OR, Grimsrud; Knut S., Forest Grove, OR, and Allen; Wayne J., Beaverton, OR, for a “data storage system with parallel array of dense memory cards and high airflow.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A data storage system with a parallel array of dense memory cards and high airflow is described. In one example, a rack-mount enclosure has a horizontal plane board with memory connectors and external interfaces. Memory cards each have a connector to connect to a respective memory connector of the horizontal plane board, each memory card extending parallel to each other memory card from the front of the enclosure and extending orthogonally from the first side of the horizontal plane board. A power supply proximate the rear of the enclosure and the first side of the horizontal plane board provides power to the memory cards through the memory card connectors and has a fan to pull air from the front of the enclosure between the memory cards and to push air out the rear of the enclosure.”

The patent application was filed on 2020-07-02 (16/946739).

Error-detecting during iterative decoding
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12308855) developed by Kwok; Zion, Burnaby, Canada, for “methods and systems for error-detecting during iterative decoding.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A system and related method, including memory and processing circuitry, which is to receive data and corresponding expected error-detecting code value. The processing circuitry processes the data in at least two portions by calculating and storing, in memory, an error-detecting code value for the respective portion. The processing circuitry is then to calculate an overall error-detecting code value based on the respective error-detecting code values for the at least two portions. When the overall error-detecting code value does not match the expected error-detecting code value the processing circuitry is to correct at least one portion and process the corrected portions by calculating an updated error-detecting code value for a respective one of the corrected portions and calculating an updated overall error-detecting code value based on the updated error-detecting code value for each corrected portions and the stored error-detecting code values.”

The patent application was filed on 2023-04-11 (18/133459).

Generating optimized combination sets for error correction in data transmission
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12301260) developed by Ji; Young Hoon, and Poon; Nathan, Vancouver, Canada, for “systems and methods for generating optimized combination sets for error correction in data transmission.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-transitory computer-readable medium, method and system, the system including processing circuitry. The processing circuitry is to generate a first matrix, perform an incident cycle optimization process using the first matrix to generate a modified first matrix, and perform an encoder gate optimization process using the modified first matrix to generate a further modified first matrix. Processing circuitry is then to generate a second matrix including the further modified first matrix as a submatrix of the second matrix, perform the incident cycle optimization process using the second matrix to generate a modified second matrix, and perform the encoder gate optimization process using the further modified first matrix and the modified second matrix to generate a further modified second matrix. Processing circuitry then configures a transmitting device that receives and encodes transmission data the using the further modified first matrix and further modified second matrix, and transmits the encoded transmission data.”

The patent application was filed on 2023-11-13 (18/507765).

Devices and methods for improving multi-stream write amplification factor
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12287730) developed by Vishwanath; Darshan Mallapur, Santa Clara, CA, Carlton; David, Pleasanton, CA, and Hughes; Jonathan, Longmont, CO, for “devices and methods for improving multi-stream write amplification factor.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A device and related method, the device including memory and processing circuitry. The memory includes sets of source memory bands and a defragmentation destination memory band. Each set of source memory bands includes source memory bands and at least one portion of each source memory band stores valid data. The processing circuitry determines a merit score corresponding to each source memory band based on one or more characteristics of portions of data of each corresponding source memory band and determines, for each set of source memory bands, a respective source memory band that corresponds to a second-highest merit score. The processing circuitry identifies a set of source memory bands that includes a source memory band corresponding to a highest second-highest merit score and stores at least one portion of valid data from the source memory bands of the identified set of source memory bands to the defragmentation destination memory band.”

The patent application was filed on 2023-12-22 (18/394104).

Irregular error correction code construction in order of weights
SK hynix NAND Product Solutions Corporation, Rancho Cordova, CA, has been assigned a patent (12273124) developed by Ji; Young Hoon, Vancouver, Canada, for “systems and methods for irregular error correction code construction in order of weights.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-transitory computer-readable medium and related method, including processing circuitry, which performs in-order error correction code construction. The processing circuitry receives a first plurality of matrices. The processing circuitry is to generate a second plurality of matrices based on at least one additive candidate matrix and each respective matrix of the first plurality of matrices. The processing circuitry then generates a third plurality of matrices based on at least one additive test matrix and each respective matrix of the second plurality of matrices. Each respective weight indicative of respective extensibility for each matrix of the second plurality of matrices is determined based on the third plurality of matrices. At least one matrix from the second plurality of matrices is then selected by processing circuitry based on the determined weights. The processing circuitry then generates an error correction code based on one of the at least one selected matrix.”

The patent application was filed on 2023-08-23 (18/237058).