R&D: Switch Merge Prone Write Buffer Cache Management for NAND Flash Memory

IEEE Transactions on Consumer Electronics has published an article written by Shailesh Kumar, Department of Computer science and Engineering, Jaypee Institute of Information Technology, Noida, Uttar Pradesh, India, Department of Computer science and Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India, School of International Biodesign SHInE, Indian Institute of Technology, Kanpur, India, and King George’s Medical University Lucknow, India, Pradeep Kumar Singh, Department of Computer science and Engineering, Madan Mohan Malaviya University of Technology, Gorakhpur, Uttar Pradesh, India, and Sumit Kumar Vaish, School of International Biodesign SHInE, Indian Institute of Technology, Kanpur, India, and King George’s Medical University Lucknow, India.

Abstract: “Nowadays, portable computing devices have become an integral part of our everyday routines. These devices necessitate storage media that possess qualities such as being lightweight, energy-efficient, compact, and shock-resistant. Consequently, NAND flash has emerged as the foremost option for fulfilling these storage needs. The primary concern with flash memory is its ’erase-then-write’ constraint. Numerous Write Buffer Cache Management Schemes have been introduced to reduce the frequency of erase operations of flash blocks. The suggested approach selects the victim block from the Write Buffer Cache (WBC) based on its Access Frequency, Size, and the Number of Sequential pages it contains. In contrast to existing methods, the suggested approach takes into consideration the sequentiality of pages within a cluster. Selecting the victim cluster based on the sequentiality of pages makes it prone to switch merge at the FTL level. Consequently, it outperforms other techniques like BPLRU, CLC, and the Dead Block Approach (DBA).“