R&D: Large Window Nonvolatile Transistor Memory for High-Density and Low-Power Vertical NAND Storage Enabled by Ferroelectric Charge Pumping

IEEE Electron Device Letters has published an article written by Zijian Zhao; Yixin Qin; Jiahui Duan; YuShan Lee; Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN, USA, Suhwan Lim; Kijoon Kim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Samsung Electronics Company Ltd., Hwaseong-si, Gyeonggi-do, Republic of Korea, Vijaykrishnan Narayanan, Department of Computer Science and Engineering, State College, The Pennsylvania State University, University Park, PA, USA, and Kai Ni, Department of Electrical Engineering, University of Notre Dame, Notre Dame, IN, USA.

Abstract: “In this work, we have developed a large memory window (MW) ferroelectric field effect transistor (FeFET) memory for vertical NAND storage. We demonstrate that: 1) by inserting a top functional layer above the ferroelectric, gate side injection pumped by ferroelectric switching event can be enhanced, thus increasing the MW; 2) inspired by the charge trap flash, SiN _X is chosen as the charge trapping layer and the proposed structures have been experimentally demonstrated to effectively increase MW; 3) the MIFIS structure demonstrates a 6V-8V MW for 11V 1μs write pulse and 8V-12V window for 15V 1μs with a SiO _X composite functional layer; 4) interestingly, the MIFIS device shows immediate read-after-write capability, which is not observed in the baseline FeFET, suggesting minor channel side injection and relaxation.“