R&D: Reading Reliability Analysis and Modeling in 1S1R Devices Based on Phase-Change Memory and Ovonic Threshold Switching Selector Integrated in Double-Patterned Self-aligned Structure

Microelectronics Reliability has published an article written by Renzo Antonelli, Univ. Grenoble Alpes, CEA, Leti, F-38000, Grenoble, France, and Univ. Grenoble Alpes, CNRS, LTM, 38054, Grenoble, France, C. De Camaret, G. Bourgeois, Z. Saghi, T. Monniez, S. Martin, N. Castellani, M. Bernard, L. Fellouh, A. Salvi, S. Gout, F. Andrieu, Univ. Grenoble Alpes, CEA, Leti, F-38000, Grenoble, France, A. Souifi, Univ. Grenoble Alpes, CNRS, LTM, 38054, Grenoble, France, and G. Navarro, Univ. Grenoble Alpes, CEA, Leti, F-38000, Grenoble, France.

Abstract: “This study investigates the impact and the reliability of the reading operation in one-selector one-resistor (1S1R) memory devices based on an Ovonic Threshold Switching (OTS) selector and Phase Change Memory (PCM) co-integrated in a Double-Patterned Self-Aligned (DPSA) structure targeting Crossbar applications. Upon reading, the SET state can face a threshold voltage (V_th) increase of more than 20% depending on the reading current and on the number of reading operations, which can lead to a bit-flip soft failure. We isolate the contributions to this increase coming respectively from the OTS and the PCM, providing an assessment protocol for the reading reliability. We model the evolution of the V_th, which allow us to extract the performance metrics such as the read window margin (RWM), the reading-cycles-to-failure, and the maximum Crossbar array size. Finally, we present the SET and RESET threshold voltage distributions before and after the reading operation.“