NXP Assigned Two Patents

Power tearing protection within NVM
NXP B.V., Eindhoven, The Netherlands, has been assigned a patent (12333162) developed by Castelnuovo; Andrea, Frey; Alexandre, Hamburg, Germany, and Ostertun; Soenke, Wedel, Germany, for a “power tearing protection within a non-volatile memory (NVM).“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory (NVM) system includes a memory array divided into physical pages, control circuitry, and a global transaction log (GTL). Each physical page is configured to store a corresponding payload and corresponding metadata for the physical page. Each entry of the GTL is configured to store a transaction descriptor identifying a transaction and a corresponding physical page used by the transaction. Each entry also has a corresponding transaction log entry (TLE) flag. The control circuitry is configured to populate the entries of the GTL in sequential order with each new transaction, and, in response to completing storing the transaction descriptor for a new transaction, program the corresponding TLE flag by toggling its logic state.”

The patent application was filed on 2023-12-13 (18/538329).

Partitioned NVM having normal read bus and verify read bus
NXP B.V., Eindhoven, The Netherlands, has been assigned a patent (12333150) developed by Storms; Maurits Mario Nicolaas, Best, The Netherlands, Choy; Jon Scott, Austin, TX, Hume; Christopher Nelson, Franklin, TN, and Strauss; Timothy, Granger, IN, for a “partitioned non-volatile memory (NVM) having a normal read bus and a verify read bus.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory (NVM) includes a daisy chained normal read bus, a daisy chained verify read bus, and a plurality of partitions. Each partition includes a portion of the daisy chained normal read bus and a portion of the daisy chained verify read bus. A memory controller receives read data in response to normal read access requests to the NVM via the daisy chained normal read bus and, in response to write access requests to the NVM, receives verify read data via the daisy chained verify read bus. A bus sharing circuit is coupled between a first partition and a second partition. The bus sharing circuit, in response to a sharing control signal, selectively repurposes portions of the daisy chained verify read bus in at least one of the partitions to communicate read data to the memory controller in response to a normal read access request to the NVM.”

The patent application was filed on 2023-12-13 (18/538451).