Macronix International Assigned Four Patents

3D flash memory module chip and method of fabricating
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (12327594) developed by Yeh; Teng-Hao, Hsinchu County, Taiwan, Lue; Hang-Ting, Hsinchu, Taiwan, for “3D flash memory module chip and method of fabricating the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A 3D flash memory module chip includes a memory chip and a control chip. The memory chip includes a plurality of tiles and a plurality of heaters. The tiles each include a plurality of 3D flash memory structures. The heaters are disposed around the 3D flash memory structures of each of the tiles. The control chip is bonded with the memory chip to drive at least one of the heaters.”

The patent application was filed on 2022-01-05 (17/569419).

High bandwidth NVM for AI inference system
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (12321603) developed by Lung; Hsiang-Lan, Ardsley, NY, and Kuo; I-Ting, Taoyuan, Taiwan, for a “high bandwidth non-volatile memory for AI inference system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A high bandwidth non-volatile memory (NVM) is described suitable for providing neural network weight data to an AI accelerator processing core or cores. An artificial intelligence (AI) inference memory device employing the high bandwidth NVM technology as described herein can comprise a logic layer die including channel logic implementing connections between a plurality of channels for conducting data to and from an accelerator core via a bus and a plurality of non-volatile memory (NVM) dies stacked vertically one above another, forming a layered vertical stack of NVM dies, each of the NVM dies including at least one memory chip and a plurality of direct vertical connections to a corresponding channel in the logic layer.”

The patent application was filed on 2023-02-22 (18/112784).

IMS memory cell, IMS method and IMS memory device
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (12283343) developed by Wang; Yun-Yuan, Kaohsiung, Taiwan, Lu; Cheng-Hsien, Taoyuan, Taiwan, Tseng; Po-Hao, Taiping Dist., Taiwan, and Lee; Ming-Hsiu, Hsinchu, Taiwan, for “IMS memory cell, IMS method and IMS memory device.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The disclosure provides an in-memory search (IMS) memory cell, an IMS method and an IMS memory device. The IMS method comprises: encoding a search data and a storage data by a first IMS encoding into a first IMS encoded search data and a first IMS encoded storage data; encoding the first IMS encoded search data by a second IMS encoding into a plurality of search voltages; encoding the first IMS encoded storage data by the second IMS encoding into a plurality of threshold voltages of a plurality of memory cells of a plurality IMS memory cells of the IMS memory device; and searching the IMS memory cells by the search voltages to generate a search result.”

The patent application was filed on 2022-12-12 (18/064303).

Memory system having planes with multibit status
Macronix International Co., Ltd., Hsinchu, Taiwan, has been assigned a patent (12277346) developed by Hung; Shuo-Nan, Kuo; Nai-Ping, Hsinchu, Taiwan, and Liu; Chien-Hsin, Tainan, Taiwan, for a “memory system having planes with multibit status.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system that is based on 3D NAND flash memory of a high capacity and/or capable of high performance is provided, which includes memory planes, each including a plane core and a specific set of resources. For each memory plane of the plurality of memory planes, the technology provides (i) a corresponding plane busy (PRDY) signal indicating a busy or a ready state of the specific set of recourses of the corresponding memory plane, and (ii) a corresponding plane in operation (PIO #) signal indicating an in operation or idle state of resources used by the plane core of the corresponding memory plane. Issuance of memory commands by a controller and execution of memory commands for a memory plane of the plurality of memory planes is selectively allowed or denied, based on status of one or more of the plurality of PRDY signals and the plurality of PIO # signals.”

The patent application was filed on 2023-09-14 (18/368292).