R&D: Reference Voltage Loop Operation Based ZQ Calibration Technique for Multi-Load High- Capacity NAND Flash Memory Interface

IEEE Access has published an article written by Jun-Ha Lee, Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, Republic of Korea, and Memory Division, Samsung Electronics Company Ltd., Hwaseong, Republic of Korea, Jun-Eun Park, Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Republic of Korea, Dong-Ho Shin, Department of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, Republic of Korea, and Memory Division, Samsung Electronics Company Ltd., Hwaseong, Republic of Korea, and Kang-Yoon Lee, Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Republic of Korea.

Abstract: “This paper proposes a novel ZQ calibration method based on a reference voltage loop operation. ZQ calibration technology improves the integrity of signals transmitted on the channel by calibrating on-die termination (ODT) and output driver strength, which vary with process, voltage, and temperature (PVT), and plays an important role in the high-speed memory environment. However, the existing ZQ calibration method was designed for a single-die configuration, which can lead to calibration errors and potential operational failures in high-load environments driven by recent high-speed, high-capacity NAND Flash memory demands. To address this issue, this paper proposes a new reference voltage loop operation based ZQ calibration method that mitigates calibration errors caused by heavy loads. The proposed technique significantly reduces the impact of load fluctuations and enables stable and accurate impedance matching by switching the calibration reference node from the heavily-loaded ZQ node to a low-load reference voltage node within the die. In addition, a 2b/Cycle SAR-based ZQ code calculation method has been introduced to increase the calibration efficiency and speed. The proposed circuit is designed using a 28nm CMOS process with a supply voltage of 1V. As a result of measurements on prototype chips, it achieved a maximum voltage error of 13mV and power consumption of 8.2mW, even under a capacitive load of 4.7μ F.“