R&D: Set Associative Address Mapping to Improve Data Throughput and Reduce Tail Latency in SSDs

Journal of Systems Architecture has published an article written by Aobo Yang, Jiaojiao Wu, Jiaxu Wu, Fan Yang, Zhibing Sha, Shiyu Zhong, Zhigang Cai, and Jianwei Liao, College of Computer and Information Science, Southwest University, Chongqing, China.

Abstract: “Solid State Drives (SSDs) have become the mainstream storage infrastructure across diverse computing systems. To access the data on the flash memory, a software component called Flash Translation Layer (FTL) is used to convert the logical address of an I/O request into the corresponding physical address, at the granularity of a page. This process is referred to as page-level address mapping in SSDs. An effective mapping method should fully utilize internal parallelism to maximize I/O throughput of the SSD device, while also paying attention to the long tail latency for guaranteeing user experience. Existing mapping approaches, however, have yet to effectively address both aspects simultaneously. Therefore, this paper proposes a set associative mapping approach, called SAMap to direct data allocation on the basis of static mapping, to improve data throughput and reducing long tail latency. Specifically, SAMap manages a number of channels into the granularity of set, and enables set associative mapping for data allocation. In the case of a write request being mapped to a specific channel by following the policy of static mapping, SAMap can forward it to any channel in the same set, by considering I/O workload balance across channels. Trace-driven experiments show that our proposal can enhance I/O data throughput by 36.0% on average and cut down the tail latency by between 28.1% and 57.0%, at the 99.99th percentile, in contrast to existing approaches.“