R&D: Comparative Analysis of NMOS-/PMOS-Based 3D Fe-NAND Using TCAD Simulation

Semiconductor Science and Technology has published an article written by Taebaek Lee, Semiconductor System Engineering, Korea University, 145 Anam-ro, Seongbuk-gu Seongbuk-gu, KR 02841, Seoul, 02841, Korea (the Republic of), and Changhwan Shin, School of Electrical Engineering, Korea University, 145 Anam-ro, Seoungbuk-gu, Engineering building #417, Seoul, 02841, Korea (the Republic of).

Abstract: “As NAND Flash technology continues to develop, traditional charge trap flash (CTF) faces important challenges like leakage currents, smaller program/erase (P/E) windows, and reliability issues. To solve these problems, ferroelectric materials, especially hafnium oxide (HfO₂), have emerged as a promising alternative for charge trapping layers in next-generation 3D Fe-NAND memory. While most research has focused on NMOS-based Fe-NAND (nFeNAND), PMOS-based Fe-NAND (pFeNAND) has received less attention. This study compares nFeNAND and pFeNAND using TCAD simulations. The results show that pFeNAND not only reduces interference with nearby cells more effectively but also shows lower leakage currents compared to nFeNAND. Additionally, pFeNAND demonstrates potential for improving 3D NAND scalability, achieving a higher on-current than nFeNAND. These findings highlight the advantages of pFeNAND as a good candidate for future memory technologies.
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