Marvell Delivers Advanced Packaging Platform for Custom AI Accelerators

Summary

• Novel multi-die packaging platform enables multi-die architectures with lower power consumption and reduced total cost 
• Industry-first modular RDL interposer offers an alternative to traditional silicon interposers and enables supply chain flexibility for data center infrastructure
• Solution is production-qualified and now entering production ramp in support of customer-specific AI accelerator designs

Marvell Technology, Inc. has expanded the packaging ecosystem for AI infrastructure with an innovative multi-die solution that lowers TCO for custom AI accelerator silicon.

The advanced packaging platform is part of the Marvell comprehensive IP portfolio for custom AI compute platforms – and enables multi-chip accelerator designs 2.8x larger than conventional single-die implementations. The company’s approach can enable more efficient die-to-die interconnect, lower power consumption, increased chiplet yields and lower product cost, and provides a manufacturing alternative to traditional interposer-based multi-chip approaches. The packaging platform has been qualified with a major hyperscaler and is now ramping in production.

In the AI era, chip packaging has become critical for increasing compute density while effectively managing power, thermal dissipation, optical I/O, signal integrity, and other factors that impact the performance and reliability in multi-die chiplet designs. Simultaneously, rising supply chain complexity and extended lead times present significant challenges for scaling advanced packaging solutions. The new Marvell packaging solution enables hyperscalers to overcome these barriers, accelerating time-to-market while offering supply chain flexibility.

This is the latest innovation in a series of advancements for customers of the firm’s custom XPU solutions. This highly optimized multi-chip packaging platform was designed from the ground up with the recently announced Marvell custom HBM and CPO solutions in mind. Taken together, Marvell is building the industry’s broadest technology platform to enable custom XPU design for the future.

“Advanced packaging is one of the primary vehicles for advancing compute density in AI clusters and cloud,” said Will Chu, SVP and GM, custom cloud solutions, Marvell. “Without it, AI infrastructure would be significantly more expensive and power-hungry. We look forward to collaborating with our partners and customers to further unlock the potential of advanced packaging.“

“Chiplets constitute one of the most dynamic segments of the semiconductor market. We anticipate that chiplet processor revenue will grow by 31% per year to reach $145 billion by 2030,” said James Sanders, senior analyst, TechInsights. “Advanced packaging technologies are critical to the evolution of chiplets, giving designers a framework in which to experiment.“

Interposers serve as the foundational layer with compute, dies, memory, and other components stacked above and communicating through the interposer. The Marvell re-distribution layer (RDL) offers a compelling alternative to traditional silicon interposers for data center applications. The firm approach integrates 1390 mm² of silicon and 4 pieces of high-bandwidth memory 3/3E (HBM3/3E) memory stacks and utilizes 6 interposer RDL layers. This enables multi-die AI accelerator solutions that are 2.8 times larger than the largest possible single-chip design. The Marvell multi-die packaging solution allows for shorter die-to-die interconnects and a modular RDL interposer.

The Marvell RDL interposer reduces design cost through its modular design. In conventional chiplets, a single interposer will span the floor space of the chips it connects well as any area between them. If 2 computing cores are on opposite sides of a chiplet package, the interposer will cover the entire space. By contrast, Marvell RDL interposers are form-fitted to individual computing dies and connected by high-bandwidth paths. Not only does this approach reduce materials, it also increases chiplet yields by enabling manufacturers to replace individual dies.

The company’s multi-die packaging platform enables the integration of passive devices to reduce potential signal noise within the chiplet package caused by the power supply. In collaboration with the packaging ecosystem, Marvell has extended the solution to support multiple components within a single package, enabling the integration of the most complex AI designs.

In addition, hyperscalers can now employ the packaging technology to build XPUs with HBM3 and HBM3E memory and Marvell is actively qualifying the technology for future HBM4 designs.

Ecosystem Quotes:
“Leading-edge packaging technologies are critical to the adoption of chiplet architectures in current and future generations of AI and accelerated compute devices,” said Dr. Mike Hung, SVP, Advanced Semiconductor Engineering (ASE). “Our close collaboration with Marvell enables us to develop solutions that deliver higher levels of performance and efficiency, while reaching a broader audience across the design ecosystem.“

“2.5D packaging technology continues to modernize heterogeneous IC packaging, enabling high-performance, cost-effective integration of multiple chiplet and memory modules,” said Kevin Engel, COO, Amkor Technology, Inc. “This technology not only increases I/O and circuit density, but also paves the way for advanced 3D structures, making it indispensable for the next generation of applications.“

“The most complicated issue in the AI/ML solution design is to create an effective power delivery network, as GPUs are increasingly using more power. SEMCO is proud to have collaborated with Marvell to create a leading power delivery solution using its custom designed silicon capacitors and passive components,” said Taegon Lee, EVP and head, t strategic marketing center, Samsung Electro-Mechanics (SEMCO). “The ecosystem approach we collectively took in developing this solution will rapidly become the norm. We look forward to continued collaboration with Marvell.“

“RDL-based chiplet integration gives Marvell the flexibility to choose the optimal process technology for each part of their design,” said CB Chang, president and CEO, Siliconware USA, Inc., a subsidiary of SPIL. “As the industry continues to move toward chiplet-based architectures, this flexibility enables more complex and efficient system integration.“

Marvell Custom Strategy
The Marvell custom platform strategy seeks to deliver breakthrough results through unique semiconductor designs and innovative approaches. By combining expertise in system and semiconductor design, advanced process manufacturing, and a comprehensive portfolio of semiconductor platform solutions and IP – including electrical and optical serializer/deserializers (SerDes), die-to-die interconnects for 2D and 3D devices, silicon photonics, co-packaged copper, custom HBM, SoC fabrics, optical IO, and compute fabric interfaces such as PCIe Gen 7 – Marvell is able to create platforms in collaboration with customers that transform infrastructure performance, efficiency and value.

Marvell is currently collaborating with 3 of the top 4 hyperscalers to develop custom XPUs and CPUs for clouds and AI clusters as well as custom network interface controllers, CXL controllers and other devices to further optimize accelerated infrastructure.