R&D: Optimized LDPC Matrices, Reducing and Redistributing 1 bits for Enhanced MAP Detection in Bit-Patterned Media Recording Systems

IEEE Access has published an article written by Thien An Nguyen, Jaejin Lee, Department of Information Communication Convergence Technology, Soongsil University, Seoul, South Korea, and Jong-Ho Lee, School of Electronic Engineering, Soongsil University, Seoul, South Korea.

Abstract: “Bit-patterned media recording (BPMR) is increasingly recognized as a leading technology for next-generation storage systems due to its potential for achieving extremely high area density. In BPMR, data is stored on discrete magnetic islands arranged in a patterned layout, enabling greater storage capacity than traditional magnetic recording techniques. However, as area density increases to meet growing data demands, the magnetic islands are positioned closer together, leading to significant two-dimensional (2D) interference. This interference complicates signal interpretation, making accurate data recovery more challenging and necessitating advanced detection methods. To address these challenges, sophisticated algorithms such as maximum a posteriori (MAP) detection have shown promise in improving data recovery by accounting for the probabilistic nature of signals and noise. MAP detection can effectively mitigate 2D interference when it incorporates extrinsic information (additional data that enhances the detection process). One way to obtain this extrinsic information is through iterative algorithms that utilize the output of self-MAP detection or decoding. Low-density parity-check (LDPC) codes are commonly employed alongside MAP detection to exploit extrinsic information. However, previous studies have shown that suboptimal parity matrix structures in LDPC decoders degrade performance, particularly when using the sum-product algorithm. In this paper, we propose an optimized approach that integrates MAP detection with LDPC decoding for BPMR systems while refining the parity check matrix structure to enhance performance. Our modifications focus on reducing the number of 1-bits to maintain low density (consistent with LDPC standards) while strategically redistributing them throughout the matrix. This optimized parity matrix structure leads to improved performance compared to previous studies.“