R&D: Controllable Floating Gate Memory Performance Through Device Structure Design

Chip has published an article written by Ruitong Bie, Ce Li, Zirui Zhang, Tianze Yu, Dongliang Yang, Binghe Liu, Linfeng Sun, Centre for Quantum Physics, Key Laboratory of Advanced Optoelectronic Quantum Architecture and Measurement (MOE), School of Physics, Beijing Institute of Technology, Beijing 100081, People’s Republic of China, and Beijing Key Lab of Nanophotonics & Ultrafine Optoelectronic Systems, School of Physics, Beijing Institute of Technology, Beijing 100081, China.

Abstract: “Floating gate memory devices based on two-dimensional materials exhibit tremendous potential for high-performance nonvolatile memory. However, the memory performance of the devices utilizing the same two-dimensional heterostructures exhibits significant differences from lab to lab, which is often attributed to variations in material thickness or interface quality without detailed exploration. Such uncontrollable performance coupled with an insufficient understanding of the underlying working mechanism hinders the advancement of high-performance floating gate memory. Here, we report controllable and stable memory performance in floating gate memory devices through device structure design under precisely identical conditions. For the first time, the general differences in polarity and on/off ratio of the memory window caused by distinct structural features are revealed and the underlying working mechanisms are clearly elucidated. Moreover, we demonstrate controllable tunneling paths that are responsible for two-terminal memory performance. The findings provide general and reliable strategy for polarity control and performance optimization of two-dimensional floating gate memory devices.“