R&D: Enhancing Reliability in Ferroelectric ScAIN NVM with AlOx Layer Insertion

IEEE Electron Device Letters has published an article written by Rui Wang, Ping Wang, Haotian Ye, Ran Feng, Xifan Xu, Bingxuan An, School of Physics, State Key Laboratory for Mesoscopic Physics and Frontiers Science Center for Nano-optoelectronics, Peking University, Beijing, China, Yuzhi Deng, College of Instrument Science and Optoelectronics Engineering, Beijing Information Science and Technology University, Beijing, China, Fang Liu, Bowen Sheng, School of Physics, State Key Laboratory for Mesoscopic Physics and Frontiers Science Center for Nano-optoelectronics, Peking University, Beijing, China, Tao Wang, School of Physics, State Key Laboratory for Mesoscopic Physics and Frontiers Science Center for Nano-optoelectronics, Peking University, Beijing, China, and School of Physics, Electron Microscopy Laboratory, Peking University, Beijing, China, Xiantong Zheng, College of Instrument Science and Optoelectronics Engineering, Beijing Information Science and Technology University, Beijing, China, Bo Shen, and Xinqiang Wang, School of Physics, State Key Laboratory for Mesoscopic Physics and Frontiers Science Center for Nano-optoelectronics, Peking University, Beijing, China.

Abstract: “Ferroelectric non-volatile memory (FeNVM) is gaining significant attention for its potential applications in data storage and neuromorphic computing. Among the promising materials for next-generation FeNVM, scandium aluminum nitride (ScAlN), has garnered attention due to its favorable ferroelectric properties and compatibility with existing Si and GaN semiconductor platforms, as well as CMOS technology. However, current ScAlN-based FeNVMs have been limited by a low V_b/V_sw (breakdown voltage to polarization switching voltage ratio) figure of merit (FOM) and inadequate endurance, hindering their widespread adoption. To overcome these limitations, we proposed an innovative ScAlN FeNVM architecture that incorporates an AlO_x interlayer deposited via atomic layer deposition (ALD). This strategic addition significantly enhances the device’s performance, achieving a competitive V_b/V_sw FOM of 1.7 and extending the endurance to up to 106 write-erase cycles. Furthermore, our design demonstrates scalability, as evidenced by the successful integration of a 20-nm-thick ScAlN layer, which supports high-density integration in future devices.“