R&D: SC-GC-LDPC for NAND Flash Memory, Construction and Decoding

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems has published an article written by Jinhong Mo, Xiongfei Zhai, Min Yu, Yi Fang, and Guojun Han, Department of School of Information Engineering, Guangdong University of Technology, Guangzhou, China.

Abstract: “With the continuous improvement of data memory density, as the common solution for error correction of NAND flash, the low-density-parity-check (LDPC) code faces more challenges, such as the increasing code length requirements, the worse raw bit error rates (RBER), and the frequently varied channels. In this paper, a new (37536,33672) spatially coupled and globally coupled LDPC (SC-GC-LDPC) code is constructed to address the above challenge, which outperforms the traditional globally coupled LDPC (GC-LDPC) code with the gaps of 0.065 dB and 0.08 dB by exploiting the layered sum-product algorithm (SPA) and the layered normalized min-sum (NMS) algorithm, respectively. In the flash channel, the SC-GC-LDPC code also shows superior error correction performance than the conventional GC-LDPC codes with 25% improvement. Due to its special structure of the check matrix, an improved two-level decoding algorithm (ITLA) and an improved two-phase decoding algorithm (ITPA) are proposed in this paper. Specifically, the algorithms exploit the adjacent subcodes to correct the faulty ones, which reduces the number of check-node-updating (CNU). For the case of single subcode errors, the simulation results show that the number of CNU is reduced by ranging from 6.64% to 31.14% by applying our proposed algorithms, leading to significant improvement of throughput. Compared with the conventional algorithms, the ITLA and ITPA only show slight performance loss. Moreover, ITPA also provides high flexibility of decoding in the NAND flash memory, which can achieve the balance between the error-correction performance and the throughput.“