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R&D: Development of High Density 3D NAND Flash Memory Using New Scaling Technologies for AI Semiconductor

In this paper, new methods that enable for device scaling and performance were introduced.

Xplore has published, in 2025 IEEE International Conference on Consumer Electronics (ICCE) proceedings, an article written by Daewoong Kang, Next Generation Semiconductor Convergence and Open Sharing System, Seoul National University, South Korea, and Soongsil University, South Korea, Minkyo Suh, Gwansun Choi, Next Generation Semiconductor Convergence and Open Sharing System, Seoul National University, South Korea, and Chung-Ang University, South Korea, and Chaeyeon Jung, Next Generation Semiconductor Convergence and Open Sharing System, Seoul National University, South Korea, and Soongsil University, South Korea.

Abstract: Scaling technology of 3D NAND flash is recently required to implement large-capacity memory and high performance due to recent demand of AI semiconductors. However, it is suffering from the critical issues such as cell current, cell to cell interference and retention characteristics. In this paper, the new methods that enable for device scaling and performance were introduced.

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