Adeia Semiconductor Technologies Assigned Patent

Adeia Semiconductor Technologies LLC, San Jose, CA, has been assigned a patent (12288771) developed by DeLaCruz; Javier A., San Jose, CA, Haba; Belgacem, Saratoga, CA, Katkar; Rajesh, Milpitas, CA, and Cheng; Pearl Po-Yee, Los Altos, CA, for an “apparatus for non-volatile random access memory stacks.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.”

The patent application was filed on 2023-11-27 (18/519538).