R&D: Thermal Optimization of 2-Terminal SOT-MRAM
Could significantly outperform conventional STT-MRAM in terms of endurance, substantially benefiting from thermal engineering.
This is a Press Release edited by StorageNewsletter.com on September 27, 2024 at 2:00 pmJournal of Applied Physics has published an article written by Haotian Su, Heungdong Kwon, William Hwang, Fen Xue, Çağıl Köroğlu, Department of Electrical Engineering, Stanford University, Stanford, California 94305, USA, Wilman Tsai; Department of Materials Science and Engineering, Stanford University, Stanford, California 94305, USA, Mehdi Asheghi; Department of Mechanical Engineering, Stanford University, Stanford, California 94305, USA, Kenneth E. Goodson, Shan X. Wang, Department of Electrical Engineering, Stanford University, Stanford, California 94305, USA, and Department of Materials Science and Engineering, Stanford University, Stanford, California 94305, USA, and Eric Pop, Department of Electrical Engineering, Stanford University, Stanford, California 94305, USA, Department of Materials Science and Engineering, Stanford University, Stanford, California 94305, USA, Department of Applied Physics, Stanford University, Stanford, California 94305, USA, and Precourt Institute for Energy, Stanford University, Stanford, California 94305, USA.
Abstract: “While magnetoresistive random-access memory (MRAM) stands out as a leading candidate for embedded nonvolatile memory and last-level cache applications, its endurance is compromised by substantial self-heating due to the high programming current density. The effect of self-heating on the endurance of the magnetic tunnel junction (MTJ) has primarily been studied in spin-transfer torque (STT)-MRAM. Here, we analyze the transient temperature response of two-terminal spin–orbit torque (SOT)-MRAM with a 1 ns switching current pulse using electro-thermal simulations. We estimate a peak temperature range of 350–450 °C in 40 nm diameter MTJs, underscoring the critical need for thermal management to improve endurance. We suggest several thermal engineering strategies to reduce the peak temperature by up to 120 °C in such devices, which could improve their endurance by at least a factor of 1000× at 0.75 V operating voltage. These results suggest that two-terminal SOT-MRAM could significantly outperform conventional STT-MRAM in terms of endurance, substantially benefiting from thermal engineering. These insights are pivotal for thermal optimization strategies in the development of MRAM technologies.“