Infineon Technologies Assigned Two Patents

Local reference voltage generator for non-volatile memory
Infineon Technologies LLC, San Jose, CA, has been assigned a patent (11978494) developed by Kim, Edwin, Devilbiss, Alan D., Jain, Kapil, Colorado Springs, CO, O’Connell, Patrick F., Monument, CO, Brodsky, Franklin, Colorado Springs, CO, Sun, Shan, Monument, CO, and Chu, Fan, Colorado Springs, CO, for a “local reference voltage generator for non-volatile memory.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A method of operating a memory device that includes the steps of receiving a read command and a target address in a non-volatile memory (NVM) array, in which the NVM array is divided into a plurality of blocks based on row and column addresses, performing a read operation on NVM cells in the target address and coupling an output of each NVM cell read to a sensing circuit, generating a local reference voltage based on a base reference voltage and an adjustment reference voltage corresponding to the target address of the NVM cells being read and a block that the NVM cells belong thereto, and offsetting the base reference voltage with the adjustment reference voltage, and coupling the local reference voltage to the sensing circuit. Other embodiments are also described.”

The patent application was filed on 2023-02-17 (18/111035).

Dynamic sensing levels for NVM devices
Infineon Technologies LLC, San Jose, CA, has been assigned a patent (11978528) developed by Shetty, Shivananda, San Jose, CA, Betser, Yoram, Mazkeret Batya, Israel, Singh, Pawan, San Jose, CA, Amato, Stefano, Mountain View, CA, and Kushnarenko, Alexander, Haifa, Israel, for a “dynamic sensing levels for nonvolatile memory devices.”

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”Systems, methods, and devices dynamically determine sensing levels for memory devices. Devices include nonvolatile memory cells included in a plurality of memory sectors, a plurality of static reference cells configured to represent a first reference value for distinguishing between memory states, and a plurality of dynamic reference cells configured to represent the first reference value after a designated amount of memory sector activity. Devices also include a comparator configured to be coupled to at least one memory cell of the plurality of memory cells and to at least two of the plurality of static reference cells and the plurality of dynamic reference cells, and further configured to determine a memory state of the at least one memory cell based, at least in part, on a second reference value determined by a combination of at least two of the plurality of static reference cells and the plurality of dynamic reference cells.”

The patent application was filed on 2022-01-28 (17/649326).