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Cadence Design Systems Assigned Patent

Memory view for NVM module

Cadence Design Systems, Inc., San Jose, CA, has been assigned a patent (11971818) developed by Gregor, Steven L., Owego, NY, and Arora, Puneet, Uttar Pradesh, India, for memory view for non-volatile memory module.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory view generator evaluates a Liberty file characterizing an NVM module to generate a memory view file for the NVM module. The memory view file includes a port alias identifying ports of the NVM module. The port alias for a set of ports of the NVM module characterizes a type of port in the set of ports. The memory view file includes a port action identifying ports of the NVM module that have a static value and a port access identifying ports of the NVM module that have a dynamic value. The memory view file has an address limit characterizing a number of words in the NVM module and an address partition characterizing address bits and data bits. The memory view file includes a read delay that defines a number of clock cycles needed to hold an address bus stable after a strobe port transitions to an inactive state.

The patent application was filed on 2022-07-13 (17/863985).

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