R&D: Program Start Bias Grouping to Compensate for Geometric Property of String in 3D NAND Flash Memory

IEEE Journal of the Electron Devices Society has published an article written by Sungju Kim; Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea, Sangmin Ahn; Sechun Park; Jongwoo Kim; NAND Design Team, Icheon-si, South Korea, and Hyungcheol Shin, Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea, and Integra Semiconductor Ltd, USA.

Abstract: “The string (STR) with various geometrical profiles in 3-D NAND flash cause the degradation of program efficiency. This is because the program speed differences among WL layers within the STR are caused by the geometrical properties observed through measurement results. In this work, we propose the method to reduce the program speed differences based on a word-line (WL) grouping in terms of threshold voltage (Vth) distribution to compensate for the program start voltage (Vstart). To address various geometrical profiles, we consider a flexible compensation method through PeakVth, i.e., the net amount of movement from the erase to the program state. PeakVth according to WL layers clearly distinguished the geometrical properties among WL layers, and through this, the linearity of PeakVth is frequently observed for specific WL layer intervals with taper profile. Utilizing this linearity, we conducted the WL grouping and successfully demonstrated Vstart compensation by applying the proposed method to each WL group through the measurement of a commercial 3-D NAND package. Moreover, the reduced WL grouping method is also contrived to relax circuit design complications and evaluated the usefulness of the proposed method.“