R&D: Random Flip Bit Aware Reading for Improving High-Density 3D NAND Flash Performance

IEEE Transactions on Circuits and Systems I:Regular Papers has published an article written by Hua Feng; Debao Wei; School of Electronics and Information Engineering, Harbin Institute of Technology, Harbin, China, Shipeng Gu; Chinese Flight Test Establishment, Xi’an, China, Zhelong Piao; Yongchao Wang; and Liyan Qiao, School of Electronics and Information Engineering, Harbin Institute of Technology, Harbin, China.

Abstract: “With the explosive growth of data storage demands, the storage density of flash memory continues to increase. However, the reliability and read performance of high-density flash memory are constantly declining. To address this issue, this study proposes a low-cost read reference voltage (RRV) calibration strategy based on random bit flips. In this study, the relationship between the random bit flips count (RFBC) of flash memory and the read reference voltage offset level (RRVOL) is characterized, and an RFBC-RRVOL conversion model is constructed. Subsequently, the characteristics of 3D flash memory RRV offset are thoroughly studied, and based on the observation results. A RRV grouping optimization scheme and RRV calibration range WL expansion scheme are proposed to achieve generalized calibration of all WLs in flash memory blocks. Experimental results indicate that the proposed strategy introduces a minimal storage overhead of only 15.26 KB, which reduces the raw bit error rate (RBER) of flash memory at the end of life (EOL) and increases the success rate of one time read to 99.89%. Such improvements greatly enhance the reliability of data storage and reading performance. These results demonstrate that the strategy has good practicality and effectiveness in addressing the reliability and read performance issues of high-density flash memory.“