STMicroelectronics Assigned Patent

STMicroelectronics S.r.l., Agrate Brianza, Italy, and STMicroelectronics (Grenoble 2) SAS, Grenoble, France, has been assigned a patent (11908514) developed by Conte; Antonino, Tremestieri Etneo, Italy, Razafindraibe; Alin, Saint Martin d’Hères, France, Tomaiuolo; Francesco, Acireale, Italy, and Mortier; Thibault, Grenoble, France, for “non-volatile phase-change memory device including a distributed row decoder with n-channel MOSFET transistors and related row decoding method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “In an embodiment, a non-volatile memory device includes a memory array including a plurality of memory portions, each memory portion having a respective plurality of memory cells arranged in rows and columns, wherein the memory portions are arranged in groups, each group of memory portions having a plurality of respective memory portions arranged in a row and a plurality of respective wordlines that extend through the respective memory portions, and wherein the memory cells of the memory portions of the group are coupled to the respective wordlines and a row decoder including a pre-decoding stage configured to execute a selection, in which it selects a wordline that extends through a group of memory portions and deselects other wordlines that extend through the group of memory portions, and a subsequent deselection, in which it deselects all the wordlines that extend through the group of memory portions, wherein the row decoder further includes, for each group of memory portions, a shared pull-up stage configured to decouple from or couple to a node at a first reference potential each wordline that extends through the group of memory portions, when the wordline is respectively selected or deselected, so as to impose on each wordline, when deselected, a deselection voltage, a plurality of pull-down stages distributed along the group of memory portions, each pull-down stage being configured to locally couple each wordline that extends through the group of memory portions, when selected, to a node at a second reference potential, so as to impose locally a selection voltage on the wordline, wherein each pull-down stage is further configured to locally decouple from the node at the second reference potential each wordline that extends through the group of memory portions, when deselected; and a number of local pull-up stages distributed along the group of memory portions, each local pull-up stage having, for each wordline that extends through the group of memory portions, a corresponding local pull-up transistor of an NMOS type.”

The patent application was filed on 2022-02-08 (17/667080).