SanDisk/WDC Assigned Fourteen Patents

NVM with adjusted bit line voltage during verify
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp. company, has been assigned a patent (11837296) developed by Lien, Yu-Chung, San Jose, CA, Yuan, Jiahui, Fremont, CA, and Kwon, Ohwon, Pleasanton, CA, for a “non-volatile memory with adjusted bit line voltage during verify.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.”

The patent application was filed on 2021-10-19 (17/505179).

Semi receiver side write training for NVM system
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp. company, has been assigned a patent (11829281) developed by Lee, Jang Woo, Seongnam-si, Korea, , Rajendra, Srinivas, Milpitas, CA, Pai, Anil, and Ramachandra, Venkatesh, San Jose, CA, for a “semi receiver side write training for non-volatile memory system.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Technology is disclosed herein for semi receiver side write training in a non-volatile memory system. The transmitting device has delay taps that control the delay between a data strobe signal and data signals sent on the communication bus. The delay taps on the transmitting device are more precise that can typically be fabricated on the receiving device (e.g., NAND memory die). However, the receiving device performs the comparisons between test data and expected data, which alleviates the need to read back the test data. After the different delays have been tested, the receiving device informs the transmitting device of the shortest and longest delays for which data was validly received. The transmitting device then sets the delay taps based on this information. Moreover, the write training can be performed in parallel on many receiving devices, which is very efficient.”

The patent application was filed on 2021-06-16 (17/348910).

Memory device including laterally perforated support pillar structures surrounding contact via structures and methods for forming
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp. company, has been assigned a patent (11812598) developed by Watanabe, Kazuto, Nagoya, Japan, for “memory device including laterally perforated support pillar structures surrounding contact via structures and methods for forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, a laterally perforated support pillar structure vertically extending through the alternating stack and the retro-stepped dielectric material portion, and a layer contact via structure laterally surrounded by the laterally perforated support pillar structure and contacting a top surface of a topmost electrically conductive layer within an area of the laterally perforated support pillar structure. Each electrically conductive layer within the area of the laterally perforated support pillar structure extends through the lateral openings.”

The patent application was filed on 2021-06-23 (17/355883).

NVM with efficient testing during erase
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp. company, has been assigned a patent (11810628) developed by Pachamuthu, Jayavel, San Jose, CA, and Lee, Dana, Saratoga, CA, for a “non-volatile memory with efficient testing during erase.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “When erasing multiple sub-blocks of a block, erase verify is performed for memory cells connected to even word lines to generate even results and for memory cells connected to odd word lines to generate odd results. The even results and the odd results are used to determine that the erase verify process successfully completed. For each NAND string of a first sub-block, a last even result for the NAND string is compared to a last odd result for the NAND string. Despite the determination that the first sub-block successfully completed erase verify, the erasing failed for the first sub-block because the number of NAND strings that have the last even result different than the last odd result is greater than a limit. The system determines that one or more additional sub-blocks also failed erasing based on and in response to determining that the first sub-block failed erasing.”

The patent application was filed on 2022-02-16 (17/673172).

3D memory device with separated contact regions and methods for forming
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp. company, has been assigned a patent (11792988) developed by Ogawa, Hiroyuki, Nagoya, Japan, and Toyama, Fumiaki, Cupertino, CA, for “three-dimensional memory device with separated contact regions and methods for forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.”

The patent application was filed on 2021-08-09 (17/397678).

NVM with updating of read compare voltages based on measured current
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp. company, has been assigned a patent (11791001) developed by Song, Yi, San Jose, CA, Yuan, Jiahui, Fremont, CA, and Zhao, Dengtao, Santa Clara, CA, for a “non-volatile memory with updating of read compare voltages based on measured current.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory system reads data from non-volatile memory cells using a set of read compare voltages to determine which data state the memory cells are in, where each data state is associated with predetermined data values. The read compare voltages are determined dynamically based on a difference between memory cell current at time of programming and memory cell current at time of reading.”

The patent application was filed on 2022-03-21 (17/699508).

3D memory device including III-V compound semiconductor channel layer and method of making
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp. company, has been assigned a patent (11778817) developed by Baraskar, Ashish Kumar, Santa Clara, CA, Makala, Raghuveer S., Campbell, CA, and Rabkin, Peter, Cupertino, CA, for “three-dimensional memory device including III-V compound semiconductor channel layer and method of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A stack including a silicon oxide layer, a germanium-containing layer, and a III-V compound semiconductor layer is formed over a substrate. An alternating stack of insulating layers and spacer material layers is formed over the III-V compound semiconductor layer. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and into the III-V compound semiconductor layer. Memory opening fill structures including a memory film and a vertical semiconductor channel are formed in the memory openings. The vertical semiconductor channels can include a III-V compound semiconductor channel material that is electrically connected to the III-V compound semiconductor layer. The substrate and at least a portion of the silicon oxide layer can be subsequently detached.”

The patent application was filed on 2020-06-25 (16/912196).

3D memory device with punch-through-resistant word lines and methods for forming
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp. company, has been assigned a patent (11778818) developed by Mochizuki, Ryo, Kasagi, Yasuo, Sano, Michiaki, Oh, Junji, Terasawa, Yujin, and Namba, Hiroaki, Yokkaichi, Japan, for “three-dimensional memory device with punch-through-resistant word lines and methods for forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An alternating stack of insulating layers and electrically conductive layers, a retro-stepped dielectric material portion overlying stepped surfaces of the alternating stack, and memory stack structures extending through the alternating stack are formed over a substrate. A patterned etch mask layer including discrete openings is formed thereabove. Via cavities through an upper region of the retro-stepped dielectric material portion by performing a first anisotropic etch process. Metal plates are selectively formed on physically exposed surfaces of a first subset of the electrically conductive layers by a selective metal deposition process. A subset of the via cavities without any metal plates therein are vertically extended downward by performing a second anisotropic etch process while the metal plates protect underlying electrically conductive layers. Via cavities can be formed without punching through electrically conductive layers. Contact via structures can be formed in the via cavities by depositing at least one conductive material therein.”

The patent application was filed on 2020-07-21 (16/934445).

3D memory device with via structures surrounded by perforated dielectric moat structure and methods of making
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp. company, has been assigned a patent (11756877) developed by Ohsawa, Kazuto, Funayama, Kota, Sakai, Hisaya, and Otsu, Yoshitaka, Yokkaichi, Japan, for “three-dimensional memory device with via structures surrounded by perforated dielectric moat structure and methods of making the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a finned dielectric moat structure including a dielectric core portion vertically extending through each layer within the alternating stack and a vertical stack of dielectric fin portions laterally extending outward from the dielectric core portion, a vertical stack of insulating plates and dielectric material plates laterally surrounded by the finned dielectric moat structure, and an interconnection via structure vertically extending through the vertical stack and contacting a top surface of an underlying metal interconnect structure.”

The patent application was filed on 2021-01-22 (17/155512).

Soft data compression for NVM
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp. company, has been assigned a patent (11757468) developed by Singla, Nihal, Punjab, India, and Sravan, A Harihara, Karnataka, India, for a “soft data compression for non-volatile memory.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An encoder of a storage medium encodes data subject to a read operation specified by a storage controller by generating a plurality of symbols representing a soft data stream corresponding to the data subject to the read operation, where each symbol of the plurality of symbols includes (i) a single-bit value number indicating whether the symbol counts 0s or 1s, and (ii) an N-bit count number indicating a bit count associated with the symbol, where N is greater than or equal to two, and the encoder of the storage medium is configured to convey the plurality of generated symbols to the storage controller via electrical interface circuitry connecting the storage medium and the storage controller.”

The patent application was filed on 2021-05-29 (17/334688).

3D memory device containing truncated channels and method of operating with different erase voltages for different bit lines
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp. company, has been assigned a patent (11758718) developed by Lien, Yu-Chung, San Jose, CA, Prakash, Abhijith, Payak, Keyur, Milpitas, CA, Yuan, Jiahui, Fremont, CA, Tseng, Huai-Yuan, San Ramon, CA, Yada, Shinsuke, and Isozumi, Kazuki, Yokkaichi, Japan, for “three dimensional memory device containing truncated channels and method of operating the same with different erase voltages for different bit lines.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.”

The patent application was filed on 2021-07-14 (17/375476).

3D memory device including discrete charge storage elements and methods for forming
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp. company, has been assigned a patent (11749736) developed by Pitner, Xue Bai, San Jose, CA, Makala, Raghuveer S., Campbell, CA, Zhou, Fei, Kanakamedala, Senaka, and Said, Ramy Nashed Bassely, San Jose, CA, for “three-dimensional memory device including discrete charge storage elements and methods for forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and memory opening fill structures located in the memory opening and including a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner. A subset of the insulating layers a lower insulating sublayer, an upper insulating sublayer overlying the lower insulating sublayer, and a center insulating sublayer located between and in contact with the lower insulating sublayer and the upper insulating sublayer.”

The patent application was filed on 2021-03-01 (17/189153).

3D memory device with hybrid staircase structure and methods of forming
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp. company, has been assigned a patent (11749600) developed by Tobioka, Akihiro, Yokkaichi, Japan, for “three-dimensional memory device with hybrid staircase structure and methods of forming the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A vertically alternating sequence of unit layer stacks is formed over a substrate. Each unit layer stacks includes an insulating layer and a spacer material layer that is formed as, or is subsequently replaced with, a first electrically conductive layer. A 2×N array of stepped surfaces is formed. Each column of two stepped surfaces other than one column is vertically extended by performing a set of processing sequences at least once. The set of processing sequences includes forming a patterned etch mask layer and etching an unmasked subset of the 2×N array. One or more patterned etch mask layer has a respective continuous opening including an entire area of a respective 2×M array of stepped surfaces that is a subset of the 2×N array of stepped surfaces. Vertical stacks of memory elements are formed through the vertically alternating sequence.”

The patent application was filed on 2021-04-07 (17/224370).

Non-volatile storage system with power on read timing reduction
SanDisk Technologies LLC, Addison, TX, a Western Digital Corp. company, has been assigned a patent (11735288) developed by Hsu, Hua-Ling Cynthia, Fremont, CA, and Li, YenLung, San Jose, CA, for a “non-volatile storage system with power on read timing reduction.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Technology is disclosed herein for loading redundancy information during a memory system power on read (POR). A memory structure has primary regions (e.g., primary columns) and a number of redundant regions (e.g., redundant columns). The status of the regions is stored in isolation latches during the POR. Initially, simultaneously all latches for primary regions are reset to used and all latches for redundant regions are reset to unused. Then, isolation latches for defective primary regions are set to unused while isolation latches for corresponding redundant regions are set to used. There is no need to individually set isolation latches for redundant regions to unused, which saves time during POR. Moreover, whenever the isolation latch for a defective primary region is set from used to unused, in parallel the isolation latch for the replacement redundant column may be set from unused to used, thereby not incurring a time penalty.”

The patent application was filed on 2022-02-16 (17/672904).