R&D: 3D NAND Flash Memory Cell Current and Interference Characteristics Improvement with Multiple Dielectric Spacer

IEEE Access has published an article written by Yun-Jae Oh, Inyoung Lee, Yunejae Suh, Department of Electronic Engineering, Soongsil University, Seoul, Republic of Korea, Daewoong Kang, Department of Next Generation Semiconductor Convergence and Open Sharing System, Seoul National University, Seoul, Republic of Korea, and Il Hwan Cho, Department of Electronic Engineering, Myongji University, Yongin-si, Republic of Korea.

Abstract: “To achieve high density, the spacer length of three dimensional (3D) NAND device has been scaled down. When the program/erase cycle repeats, problems such as electrons accumulation in the inter-cell region are occurred. To solve this problem, a method of replacing the spacer region material of 3D NAND device with a low-k materials has been proposed. In 3D NAND, carrier’s lateral spreading occurs since all cells in the string share a same trap layer. In this work, we observed the change of cell current (Icell) and interference characteristic after retention time on various dielectric constant of spacer region conditions. These two factors exhibit a trade-off characteristic. In this paper, we suggested the appropriate range of dielectric constant value. Based on this observation, we have proposed a suitable range of dielectric constants and suggested the Si3N4/ Air / Si3N4(N/A/N) multiple dielectric spacer structure to improve both Icell and interference characteristics. In addition, performance improvement can be obtained through high-k / low-k / high-k multiple dielectric spacer structure. Improving the retention characteristics of 3D NAND flash memories through the proposed structure will contribute to improving the reliability of memory devices.“