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eMemory Technology Assigned Two Patents

Erasable programmable single-poly NVM cell and associated array structure, anti-fuse memory, memory array, and programming method of anti-fuse memory device for preventing leakage current and program disturbance

Erasable programmable single-poly NVM cell and associated array structure
eMemory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11818887) developed by Chen, Hsueh-Wei, Hsiao, Woan-Yun, Chen, Wei-Ren, and Sun, Wein-Town, Hsinchu County, Taiwan, for erasable programmable single-poly non-volatile memory cell and associated array structure.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.

The patent application was filed on 2022-03-04 (17/686573).

Anti-fuse memory, memory array, and programming method of anti-fuse memory device for preventing leakage current and program disturbance
eM
emory Technology Inc., Hsin-Chu, Taiwan, has been assigned a patent (11783905) developed by Lee, Chieh-Tse, Yen, Ting-Yang, Huang, Cheng-Da, and Lin, Chun-Hung, Hsinchu County, Taiwan, for anti-fuse memory device, memory array, and programming method of an anti-fuse memory device for preventing leakage current and program disturbance.

The abstract of the patent published by the U.S. Patent and Trademark Office states: “When a driving circuit of an anti-fuse memory device programs a selected anti-fuse memory cell, voltage differences between unselected bit lines and unselected anti-fuse control lines would be eliminated or decreased to an acceptable value by floating unselected anti-fuse control lines or by applying a second control line voltage to the unselected anti-fuse control lines. Leakage currents flowing from unselected bit lines through ruptured anti-fuse transistors of the anti-fuse memory device to the unselected anti-fuse control lines would be decreased or eliminated, and program disturbance would be avoided.

The patent application was filed on 2021-09-08 (17/469828).

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