GlobalFoundries U.S. Assigned Six Patents

Ferroelectric NVM device and integration schemes
GlobalFoundries U.S. Inc., Malta, NY, has been assigned a patent (11825663) developed by Müller, Johannes, Melde, Thomas, Dünkel, Stefan, Dresden, Germany, and Richter, Ralf, Radebeul, Germany, for “ferroelectric nonvolatile memory device and integration schemes.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A nonvolatile memory device is provided, the device comprising a ferroelectric memory capacitor arranged over a first active region contact of a first transistor and a gate contact of a second transistor, whereby the ferroelectric memory capacitor at least partially overlaps a gate of the first transistor.”

The patent application was filed on 2021-08-17 (17/403880).

Memory with high-accuracy reference-free multi-inverter sense circuit and associated sensing method
GlobalFoundries U.S. Inc., Malta, NY, has been assigned a patent (11735257) developed by Gaul, Nishtha, Halfmoon, NY, Paul, Bipul C., Mechanicville, NY, and Jaiswal, Akhilesh R., Falls Church, VA, for “memory with high-accuracy reference-free multi-inverter sense circuit and associated sensing method.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “Disclosed is a memory structure with reference-free single-ended sensing. The structure includes an array of non-volatile memory (NVM) cells (e.g., resistance programmable NVM cells) and a sense circuit connected to the array via a data line and a column decoder. The sense circuit includes field effect transistors (FETs) connected in parallel between an output node and a switch and inverters connected between the data line and the gates of the FETs, respectively. To determine the logic value of a stored bit, the inverters are used to detect whether or not a voltage drop occurs on the data line within a predetermined period of time. Using redundant inverters to control redundant FETs connected to the output node increases the likelihood that the occurrence of the voltage drop will be detected and captured at the output node, even in the presence of process and/or thermal variations. Also disclosed is a sensing method.”

The patent application was filed on 2021-07-20 (17/380093).

Memory cell having free ferromagnetic material layer with curved, non-planar surface and methods of making such memory cells
GlobalFoundries U.S. Inc., Santa Clara, CA, has been assigned a patent (11682514) developed by Dixit, Hemant, Halfmoon, NY, Naik, Vinayak Bharat, and Yamane, Kazutaka, Singapore, Singapore, for “memory cell having a free ferromagnetic material layer with a curved, non-planar surface and methods of making such memory cells.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An illustrative memory cell disclosed herein includes a bottom electrode, a top electrode positioned above the bottom electrode and an MTJ (Magnetic Tunnel Junction) structure positioned above the bottom electrode and below the top electrode. In this example, the MTJ structure includes a first ferromagnetic material layer positioned above the bottom electrode, a non-magnetic insulation layer positioned above the first ferromagnetic material layer and a second ferromagnetic material layer positioned on the non-magnetic insulation layer, wherein there is a curved, non-planar interface between the non-magnetic insulation layer and the ferromagnetic material layer.”

The patent application was filed on 2020-08-19 (16/997065).

NVM structure using semiconductor layer as floating gate and bulk semiconductor substrate as channel region
GlobalFoundries U.S. Inc., Santa Clara, CA, has been assigned a patent (11631772) developed by Melde, Thomas, Dünkel, Stefan, and Richter, Ralf, Dresden, Germany, for “non-volatile memory structure using semiconductor layer as floating gate and bulk semiconductor substrate as channel region.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A non-volatile memory (NVM) structure includes a first memory device including: a first inter-poly dielectric defined by an isolation layer over a first semiconductor layer over an insulator layer (SOI) stack over a bulk semiconductor substrate, a first tunneling insulator defined by the insulator layer, a first floating gate defined by the semiconductor layer of the SOI stack, and a first channel region defined in the bulk semiconductor substrate between a source region and a drain region. The memory device may also include a control gate over the SOI stack, an erase gate over a source region in the bulk substrate, and a bitline contact coupled to a drain region in the bulk substrate. The NVM structure may also include another memory device similar to the first memory device and sharing the source region.”

The patent application was filed on 2021-01-13 (17/147684).

Multi-level ferroelectric memory cell
Globalfoundries U.S.. Inc., Malta, NY, has been assigned a patent (11621269) developed by Frougier, Julien, Albany, NY, and Xie, Ruilong, Niskayuna, NY, for a “multi-level ferroelectric memory cell.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present disclosure relates to semiconductor structures and, more particularly, to a multi-level ferroelectric memory cell and methods of manufacture. The structure includes: a first metallization feature, a tapered ferroelectric capacitor comprising a first electrode, a second electrode and ferroelectric material between the first electrode and the second electrode, the first electrode contacting the first metallization feature, and a second metallization feature contacting the second electrode.”

The patent application was filed on 2019-03-11 (16/298413).

NVM cell arrays with sectioned active region and methods of manufacturing
GlobalFoundries U.S. Inc., Santa Clara, CA, has been assigned a patent (11538815) developed by Restrepo, Oscar D., Clifton Park, NY, Banghart, Edmund K., Pittsford, NY, and Taylor, William, Clifton Park, NY, for a “non-volatile memory cell arrays with a sectioned active region and methods of manufacturing thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “TStructures for an array of non-volatile memory cells and methods of forming a structure for an array of non-volatile memory cells. An active region of a substrate includes a first section having a side edge and a second section extending laterally from the side edge. The first section of the active region has a first length dimension in a direction parallel to the first side edge. The second section has a second length dimension in the direction parallel to the first side edge. The second length dimension is less than the first length dimension. A fin is positioned on the substrate in the second section of the active region. A gate structure extends over the fin and the second section of the active region.”

The patent application was filed on 2020-07-22 (16/935691).