R&D: 7-Bit/2Cell (X3.5), 9-Bit/2Cell (X4.5) NAND Flash Memory, Half Bit Technology

2023 IEEE International Memory Workshop (IMW) has published an article written by Noboru Shibata, Hironori Uchikawa, Kioxia Corporation, Institute of Memory Technology Research & Development, Japan, Taira Shibuya, Kenri Nakai, Kosuke Yanagidaira, Memory Div, Kioxia Corporation, Japan, and Hirofumi Inoue, Memory Development Strategy Div, Kioxia Corporation, Japan.

Abstract: “In this work, a 3. 5bit/cell (X3.5) flash memory is introduced to achieve a lower giga-byte cost with high reliability and performance. Accordingly, 7-bit data are stored in two memory cells with 12-level Vth distributions. The X3.5 Programming method does not require the complex approach used in QLC and can easily be handled by NAND controller. QLC needs a more powerful ECC than TLC; hence, increasing the size of the ECC parity for QLC enlarges the die size. However, the same ECC parity size as TLC can be applicable to X3.5. An X3.5 die size with a TLC ECC is only 6.3% bigger than QLC. By contrast, X3.5 Program performance is 2.3 times faster than QLC with the QLC reliability criteria, which is relaxed from the TLC reliability criteria. If the size of the ECC parity is reduced to that of 32nmMLC, X3.5 die size will be close to that of QLC, while X3.5 Program performance will be 1.6 times faster than that of QLC. Moreover, X3.5 will meet the TLC reliability criteria. In addition to expanding X3.5 technologies, 4.5 bit/cell (X4.5) with a 24-level Vth distributions is also possible, which is suitable for cold storage applications.“