Technology CAD Simulation Data for 3D X-DRAM from NEO Semiconductor

NEO Semiconductor, developer of technologies for 3D NAND flash and DRAM memory, announced findings of 3D X-DRAM simulations.

Semiconductor manufacturers and engineers use TCAD to simulate emerging technologies and optimize new products.

Explorations of TCAD models and simulations reveal that 3D X-DRAM supports:

TCAD simulations show the company’s 3D X-DRAM delivers performances of high speed, high sensing margins, long retention times, and high endurance cycles.

<1V (volt) operation voltage
<3ns (nanosecond) write time (cell level)
>20 uA (microampere) sensing margin
>100ms data retention time
>10ˆ16 endurance cycles

“Semiconductor manufacturers rely on TCAD tools to accelerate development and optimize products using virtual experiments rather than physical ones,” said Andy Hsu, founder and CEO, NEO Semiconductor and a technology inventor with more than 120 U.S. patents. “We use these same tools to create models and run simulations demonstrating the feasibility of adopting 3D X-DRAM technology to bring 3D DRAM products to market.”

3D X-DRAM uses iFloating Body Cell (FBC) technology with 1 transistor and zero capacitors for each data bit. A simple 3D structure makes 3D X-DRAM less risky and costly than 3D DRAM alternatives. Manufacturing 3D X-DRAM involves a self-aligned, 3D NAND-like process with high yields. The company estimates 3D X-DRAM achieves 128Gb density with 230 layers – 4x better than 2D DRAM.

“A new memory architecture with 3D DRAM technology will represent the future of memory in order to accelerate and scale DRAM to new levels,” said Jay Kramer, president, Network Storage Advisors Inc. “NEO Semiconductor is leading the way with an innovative design that not only will address new levels of performance, reduced power consumption and smaller footprint but will be the first to power the next generation of memory that can enable new applications in the marketplace.“

The company will give an invited speech about 3D X-DRAM in the 16^th IEEE International Memory Workshop (IMW) being held May 12-15, 2024 in Seoul, Republic of Korea. Hsu will release additional ‘TCAD Simulation Results’ for this technology.