IEDM Conference: Avalanche Schowcasing Dual QSPI 8Gb Spin Transfer Torque MRAM Solutions for Space Applications

Avalanche Technology continues to demonstrate industry leadership of both technology development and commercialization of an advanced next-gen MRAM platform solutions for the space Industry.

The company will present ‘Dual QSPI 8Gb STT-MRAM Solutions for Space Applications’ at the 2023 IEEE International Electron Devices Meeting (IEDM), held in San Francisco, CA December 9-13. The presentation will provide attendees with an overview of the technical specs, design considerations, and real-world applications of the company‘s Spin Transfer Torque (STT) MRAM devices for space applications. The firm invites industry experts, researchers, and space technology enthusiasts to explore the potential of this innovation.

IEDM is a forum for reporting technological breakthroughs in the areas of semiconductor and electronic device technology, design, manufacturing, physics, and modeling. It is the flagship conference for nanometer-scale CMOS transistor technology, advanced memory, displays, sensors, MEMS devices, novel quantum and nano-scale devices and phenomenology, optoelectronics, devices for power and energy harvesting, high-speed devices, as well as process technology and device modeling and simulation. Within this array of technology sectors, the forum will contain topics from nascent technology development efforts through more proven product implementations for this burgeoning non-volatile memory category, with no application more compelling than the incredibly challenging environment of space. While satellite designers have learned to build Rube Goldberg-esque hardware and software architectures to deal with the radiation susceptibility challenges of legacy memory devices, the resulting bloated, power hungry and expensive hardware has impeded the industry’s ability to innovate.

With the production release of the firm’s STT-MRAM solutions, optimized for reliability, density, endurance, retention, and radiation resilience, all at low power, the trade space Pareto for space architectures has been upended. System designers can now develop SWaP-optimized common hardware platforms with pin compatible scalability for density, qualification and screening from 8Gb soon down to 64Mb, for storage and multi-mission configurability of advanced FPGAs and SoCs.

Dr. Yiming Huai, CTO, Avalanche, known as the ‘Father of STT MRAM’, expressed excitement about the upcoming presentation, stating: “Our team has dedicated extensive efforts to develop a memory solution, based on Avalanche leading proprietary pMTJ and chip design technologies, tailored for the uniquely demanding reliability and environmental rigors of space applications. This family of 22nm STT MRAM devices manufactured at our partner foundry UMC finally realizes the full potential of STT-MRAM as an enabling technology for satellite system and network-level innovation, and we are eager to showcase its capabilities at the prestigious IEDM conference.“

Avalanche Gen 3 Space Grade MRAM
The Gen 3 Space Grade MRAM family is offered as a standard product in Parallel with asynchronous SRAM-compatible timing and Dual QSPI high speed Serial interface, in various density options from 1 to 8Gb. Designed for high-reliability with multibit error correction and industry 10^16 write cycle endurance, data is always non-volatile. The devices are offered in small footprint packaging and extended operating temperature range (-40°C to 125°C) with a JEDEC qualification flow, where every device goes through a 48-hour burn-in before being shipped to customers. There are additional qualification screening and packaging options available through partners.