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STMicroelectronics Assigned Three Patents

Phase-change memory with insulating layer on cavity sidewall, memory device, high density array, in memory computing

Phase-change memory with insulating layer on cavity sidewall
STMicroelectronics (Crolles 2) SAS, Crolles, France, and STMicroelectronics (Rousset) SAS, Rousset, France, has been assigned a patent (11800821) developed by Boivin, Philippe, Venelles, France, Benoit, Daniel, Grenoble, France, and Berthelon, Remy, Saint Martin d’Heres, France, for a phase-change memory with an insulating layer on a cavity sidewall.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”The present disclosure concerns a phase-change memory manufacturing method and a phase-change memory device. The method includes forming a first insulating layer in cavities located vertically in line with strips of phase-change material, and anisotropically etching the portions of the first insulating layer located at the bottom of the cavities, and a phase-change memory device including a first insulating layer against lateral walls of cavities located vertically in line with strips of phase-change material.

The patent application was filed on 2022-07-01 (17/856711).

Memory device
STMicroelectronics S.r.l., Agrate Brianza, Italy, has been assigned a patent (11798630) developed by Carissimi, Marcella, Bergamo, Italy, Disegni, Fabio Enrico Carlo, Spino d’adda, Italy, Auricchio, Chantal, Milan, Italy, Torti, Cesare, Pavia, Italy, Manfre’, Davide, Pandion, Italy, Capecchi, Laura, Vedano al Lambro, Italy, Calvetti, Emanuela, Villa d’Adda, Italy, and Zanchi, Stefano, Milan, Italy, for a memory device.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory device includes programmable memory cells and a programming circuit for programming a selected memory cell to a target logic state by applying one or more programming current pulses. A temperature sensor operates to sense a temperature of the memory device. A reading circuit reads a current logic state of the selected memory cell after a predetermined programming current pulse of the programming current pulses. The reading circuit includes a sensing circuit that senses a current logic state of the selected memory cell according to a comparison between a reading electric current depending on the current logic state of the selected memory cell and a reference current. An adjusting circuit adjusts one or the other of the reading electric current and the reference electric current to be provided to the sensing circuit according to the temperature of the memory device.

The patent application was filed on 2021-08-20 (17/407903).

High density array, in memory computing
STMicroelectronics International N.V., Geneva,
Switzerland, has been assigned a patent (11798615) developed by Grover, Anuj, New Delhi, India, and Roy, Tanmoy, Greater Noida, India, for a high density array, in memory computing.

The abstract of the patent published by the U.S. Patent and Trademark Office states: ”A memory cell that performs in-memory compute operations, includes a pair of cross-coupled inverters and a pair of transistors for selective performance of read/write/hold operations associated with logic states of the pair of cross-coupled inverters. The memory cell further includes a set of transistors that are gate coupled to and symmetrically arranged about the pair of cross coupled inverters. Output nodes of the memory cell are located at terminals of the set of transistors and provide output based on logic states of the pair of cross coupled inverters and input nodes provided between pairs of the set of transistors. A memory cell array may be generated having a high density arrangement memory cells that can perform in-memory compute operations. The memory cells can be arranged as a neural network including a set of memory cell networks that provide logic output operations based on logic states of the respective memory cells.

The patent application was filed on 2022-04-15 (17/721956).

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