R&D: Hybrid Program Algorithm Enables Significant Reduction in Write Latency and Power Consumption for Multilevel Phase Change Memory

IEEE Transactions on Electron Devices has published an article written by Qingyu Wu, National Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China, and University of Chinese Academy of Sciences, Beijing, China, Chenchen Xie, National Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China, and Shanghai Nanotechnology Promotion Center, Shanghai, China, Xi Li, Houpeng Chen, Li Xie, Qian Wang, National Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China, and Shanghai Xinchu Integrated Circuit Corporation, Shanghai, China, Zhenchao Sui, Peking University, Beijing, China, and Semiconductor Manufacturing International (Beijing) Corporation, Beijing, China, Sannian Song, and Zhitang Song, National Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai, China, and Shanghai Xinchu Integrated Circuit Corporation, Shanghai, China.

Abstract: “Multilevel cell (MLC) phase change memory (PCM) not only helps in reducing the cost-per-bit of novel nonvolatile memory but also proves to be well-suited for neuromorphic computing, due to its continuously adjustable conductance. However, conventional MLC PCM devices suffer from significant bottlenecks associated with process variability, device loss, energy efficiency, and speed, which hinder their further development. This article proposes a hybrid programming algorithm for MLC PCM devices that employs one-shot preprogram and graded iterations to speed up the convergence of intermediate conductance while consuming lower power and experiencing less device loss. Test experiments conducted on a 64M-cell PCM chip, operating at 4 bits/cell, demonstrate that the proposed scheme is effective in reducing program time and power consumption by 82.3% and 82.6%, respectively, compared to traditional program schemes. Furthermore, the classification of handwritten MNIST datasets using PCM synapses yielded an accuracy of 94.22%, which was further improved to 97.32% by limiting the weight range through software optimization.“