Netlist Assigned Two Patents

Uniform memory access in system having plurality of nodes
Netlist, Inc., Irvine, CA, has been assigned a patent (11768769) developed by Lee, Hyun, and Ryu, Junkil, Irvine, CA, for a “uniform memory access in a system having a plurality of nodes.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “The present application presents a Uniform Memory Access (UMA) network including a cluster of UMA nodes. A system in a UMA node comprises persistent memory, non-persistent memory, a node control device operatively coupled to the persistent memory and the non-persistent memory, a local interface for interfacing with the local server in the respective UMA node, and a network interface for interfacing with the UMA network. The node control device is configured to translate between a local unified memory access (UMA) address space accessible by applications running on a local server and a global UMA address space that is mapped to a physical UMA address space. The physical UMA address space includes physical address spaces associated with different UMA nodes in the cluster of UMA nodes. Thus, a server in the UMA network can access the physical address spaces at other UMA nodes without going through the servers in the other UMA nodes.”

The patent application was filed on 2021-11-09 (17/522705).

Memory module with timing-controlled data buffering
Netlist, Inc., Irvine, CA, has been assigned a patent (11762788) developed by Lee; Hyun, Ladera Ranch, CA, and Bhakta; Jayesh R., Cerritos, CA, for a “memory module with timing-controlled data buffering.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signal.”

The patent application was filed on 2020-12-07 (17/114478).