TC Lab Assigned Patent
3D memory array clusters and resulting memory architecture
By Francis Pelletier | October 24, 2023 at 2:00 pmTC Lab, Inc., Gilroy, CA, has been assigned a patent (11763872) developed by Bateman; Bruce L., Fremont, CA, for “3D memory array clusters and resulting memory architecture.“
The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory architecture for 3-dimensional thyristor cell arrays is disclosed. Thyristor memory cells are connected in a 3-dimensional cross-point array to form a bit line cluster. The bit line clusters are connected in parallel to sense amplifier and write circuits through multiplexer/demultiplexer circuits. Control circuits select one of the bit line clusters during a read or write operation while the non-selected bit line clusters are not activated to avoid disturbs and power consumption in the non-selected bit line clusters. The bit line clusters, multiplexer/demultiplexer circuits, and sense amplifier and write circuits from a memory array tile (MAT).”
The patent application was filed on 2021-09-28 (17/488148).
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