eMemory Technology Assigned Four Patents

Memory structure and operation method thereof
eMemory Technology Inc., Hsinchu, Taiwan, has been assigned a patent (11751398) developed by Hsu; Chia-Jung, Hsiao; Woan-Yun, and Sun; Wein-Town, Hsinchu County, Taiwan, for “memory structure and operation method thereof.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory structure including a substrate, a gate structure, a charge storage layer, and a first control gate is provided. The substrate has a fin portion. A portion of the gate structure is disposed on the fin portion. The gate structure and the fin portion are electrically insulated from each other. The charge storage layer is coupled the gate structure. The charge storage layer and the gate structure are electrically insulated from each other. The first control gate is coupled to the charge storage layer. The first control gate and the charge storage layer are electrically insulated from each other.”

The patent application was filed on 2021-08-12 (17/401262).

Memory device having reference memory array structure resembling memory array structure, and methods of operating
eMemory Technology Inc., Hsinchu, Taiwan, has been assigned a patent (11749372) developed by Yang; Cheng-Te, Hsinchu County, Taiwan, for “memory device having reference memory array structure resembling data memory array structure, and methods of operating the same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A memory device includes a data memory array, a reference memory array and a detection circuit. The reference memory array includes (N/2+1) bit lines, (N/2) source lines and reference cells, N being a positive even integer. Each row of reference cells includes a (2n−1)th reference cell and a (2n)th reference cell. The (2n−1)th reference cell includes a first terminal coupled to an nth bit line, and a second terminal coupled to an nth source line, n being a positive integer less than N/2+1. The (2n)th reference cell includes a first terminal coupled to an (n+1)th bit line, and a second terminal coupled to the nth source line. The detection circuit compares a data current outputted from the data memory array and a reference current outputted from the reference memory array to determine a data state of a memory cell.”

The patent application was filed on 2021-12-10 (17/547240).

Antifuse-type one time programming memory cell and cell array structure with same
eMemory Technology Inc., Hsinchu, Taiwan, has been assigned a patent (11735266) developed by Chen; Lun-Chun, Chen; Jiun-Ren, Ho; Ping-Lung, and Chen; Hsin-Ming, Hsinchu County, Taiwan, for “antifuse-type one time programming memory cell and cell array structure with same.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “An antifuse-type one time programming memory cell includes a select device, a following device and an antifuse transistor. A first terminal of the select device is connected with a bit line. A second terminal of the select device is connected with a first node. A select terminal of the select device is connected with a word line. A first terminal of the following device is connected with the first node. A second terminal of the following device is connected with a second node. A control terminal of the following device is connected with a following control line. A first drain/source terminal of the antifuse transistor is connected with the second node. A gate terminal of the antifuse transistor is connected with an antifuse control line. A second drain/source terminal of the antifuse transistor is in a floating state.”

The patent application was filed on 2021-11-29 (17/536414).

Short channel effect based random bit generator
eMemory Technology Inc., Hsinchu, Taiwan, has been assigned a patent (11709656) developed by Hsu; Ching-Hsiang, Hsinchu County, Taiwan, for a “short channel effect based random bit generator.“

The abstract of the patent published by the U.S. Patent and Trademark Office states: “A random bit generator includes a voltage source, a bit data cell, and a sensing control circuit. The voltage source provides a scan voltage during enroll operations. The data cell includes a first transistor and a second transistor. The first transistor has a first terminal coupled to a first bit line, a second terminal coupled to the voltage source, and a control terminal. The second transistor has a first terminal coupled to a second bit line, a second terminal coupled to the voltage source, and a control terminal. The sensing control circuit is coupled to the first bit line and the second bit line, and outputs a random bit data according to currents generated through the first transistor and the second transistor during an enroll operation of the bit data cell.”

The patent application was filed on 2019-04-02 (16/373599).