R&D: Stochastic Computing-Based Computation-in-Memory (SC CiM) Architecture for DNNs and Hierarchical Evaluations of NVM Error and Defect Tolerance

2023 IEEE International Memory Workshop (IMW) has published an article written by Takuto Nishimura, Yuya Ichikawa, Akira Goda, Naoko Misawa, Chihiro Matsui, and Ken Takeuchi, Dept. of Electrical Engineering and Information Systems, The University of Tokyo, Japan.

Abstract: “A Stochastic Computing-based Computation-inMemory architecture (SC CiM) with non-volatile memory (NVM) stochastic weights has been proposed. Both of the input and weight values are converted into stochastic bit streams. The multiply-and-accumulate (MAC) operation of the SC multiplication is performed in memory. The computational accuracy is characterized for Resnet-56 and CIFAR-10, with the bit error rate (BER) range from 10−4 to 10−2 representing the actual NVM characteristics. The effects of NVM BER are analyzed hierarchically at all computational layers (bit streams, MAC calculation and DNN inference) and compared both qualitatively and quantitatively with the conventional CiM. The results show the excellent robustness of the proposed SC CiM architecture in the wide range of BER. The tolerance to the manufacturing defects is even better than that of the conventional CiM. Furthermore, the desired weight distributions are discussed by exploiting the unique behaviors against NVM BER in the SC CiM.“